參數(shù)資料
型號: ZL30102QDG1
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP64
封裝: 10 X 10 MM, 1 MM HEIGHT, LEAD FREE, MS-026ACD, TQFP-64
文件頁數(shù): 1/48頁
文件大?。?/td> 944K
代理商: ZL30102QDG1
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2005, Zarlink Semiconductor Inc. All Rights Reserved.
Features
Synchronizes to clock-and-sync-pair to maintain
minimal phase skew between an H.110 primary
master clock and a secondary master clock
Supports Telcordia GR-1244-CORE Stratum 4 and
4E
Supports ITU-T G.823 and G.824 for 2048 kbit/s
and 1544 kbit/s interfaces
Supports ANSI T1.403 and ETSI ETS 300 011 for
ISDN primary rate interfaces
Simple hardware control interface
Manual and Automatic hitless reference switching
between any combination of valid input reference
frequencies
Accepts three input references and synchronizes
to any combination of 8 kHz, 1.544 MHz,
2.048 MHz, 8.192 MHz or 16.384 MHz inputs
Provides a range of clock outputs: 1.544 MHz,
2.048 MHz, 3.088 MHz, 6.312 MHz, 16.384 MHz
and either 4.096 MHz and 8.192 MHz or
32.768 MHz and 65.536 MHz
Provides 5 styles of 8 kHz framing pulses
Holdover frequency accuracy of 1x10
-7
Provides Lock, Holdover and selectable Out of
Range indication
Attenuates wander from 1.8 Hz
Less than 0.6 ns
pp
intrinsic jitter on all output
clocks
External master clock source: Clock Oscillator or
Crystal
Applications
Synchronization and timing control for multi-trunk
DS1/ E1 terminal systems such as DSLAMs,
Gateways and PBXs
Clock and frame pulse source for H.110 CT Bus,
ST-BUS, GCI and other time division multiplex
(TDM) buses
November 2005
Ordering Information
ZL30102QDG
ZL30102QDG1 64 pin TQFP* Trays, Bake & Drypack
*Pb Free Matte Tin
-40
°
C to +85
°
C
64 pin TQFP
Trays, Bake & Drypack
ZL30102
T1/E1 Stratum 4/4E Redundant System
Clock Synchronizer for DS1/E1 and H.110
Data Sheet
Figure 1 - Functional Block Diagram
Reference
Monitor
Mode
Control
Virtual
Reference
IEEE
1149.1a
TIE
Corrector
Enable
State Machine
Frequency
Select
MUX
TIE
Corrector
Circuit
MODE_SEL1:0
TCK
REF1
REF2
RST
REF_SEL1:0
TIE_CLR
C1.5o
C3o
C4/C65o
C8/C32o
C16o
F4/F65o
F8/F32o
F16o
OSCo
OSCi
Master Clock
TDO
REF0
TDI
TMS
TRST
HOLDOVER
FASTLOCK
HMS
LOCK
REF_FAIL0
REF_FAIL1
REF_FAIL2
DPLL
OUT_SEL
OOR_SEL
C2o
REF2_SYNC
SEC_MSTR
E1
Synthesizer
DS1
Synthesizer
MUX
DS2
Synthesizer
C6o
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