參數(shù)資料
型號： ZL30102QDG1
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 通信及網(wǎng)絡
英文描述： T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP64
封裝： 10 X 10 MM, 1 MM HEIGHT, LEAD FREE, MS-026ACD, TQFP-64
文件頁數(shù)： 14/48頁
文件大?。?/td> 944K
代理商： ZL30102QDG1
ZL30102
Data Sheet
14
Zarlink Semiconductor Inc.
Figure 6 - E1 Out-of-Range Thresholds for OOR_SEL=1
In addition to the monitoring of the REF2 reference signal the companion REF2_SYNC input signal is also
monitored for failure (see Figure 7).
Sync Ratio Monitor (SRM)
: This monitor detects if the REF2_SYNC signal is an 8 kHz signal. It also checks the
number of REF2 reference clock cycles in a single REF2_SYNC frame pulse period to determine the integrity of the
REF2_SYNC signal, for example there must be exactly 256 clock cycles of a 2.048 MHz REF2 reference clock in a
single REF2_SYNC 8 kHz frame pulse period to validate the REF2_SYNC signal. If the REF2 and REF2_SYNC
inputs are selected for synchronization and the Sync Ratio Monitor detects a failure, the DPLL will abandon the
mechanism of aligning the output frame pulse to the REF2_SYNC pulse. Instead only the REF2 reference will be
used for synchronization.
Figure 7 - REF2_SYNC Reference Monitor
3.3 Time Interval Error (TIE) Corrector Circuit
The TIE Circuit eliminates phase transients on the output clock that may occur during reference switching or the
recovery from Holdover mode to Normal mode.
On recovery from Holdover mode (dependent on the HMS pin) or when switching to another reference input, the
TIE corrector circuit measures the phase delay between the current phase (feedback signal) and the phase of the
selected reference signal. This delay value is stored in the TIE corrector circuit. This circuit creates a new virtual
reference signal that is at the same phase position as the feedback signal. By using the virtual reference, the PLL
minimizes the phase transient it experiences when it recovers from Holdover mode.
0 ppm
+50 ppm
-50 ppm
0
50
130
100
50
80
-50
-150
-150
-100
0
-50
50
150
Frequency offset [ppm]
Out of Range
Out of Range
Out of Range
In Range
In Range
In Range
C20
100
-100
-130
180
150
-50
-80
-180
C20
C20
-200
200
C20: 20 MHz master oscillator clock
C20 Clock Accuracy
SYNC
Reference
Monitor
Circuit
to DPLL
REF2_SYNC
REF2
frequency
REF2
相關(guān)PDF資料
PDF描述
ZL30102 T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110
ZL30102QDG T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110
ZL30105QDG1 T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110
ZL30105 Power Clamp On Multimeter; DMM Type:Clamp; No. of Digits/Alpha:3-3/4; DMM Response Type:True RMS; Approval Categories:CAT III 600V; Calibrated:No; Current Measuring Range:0-400.0A; Current Setting AC:400A RoHS Compliant: NA
ZL30105QDG Digital Clamp-On Meter; DMM Type:Clamp; No. of Digits/Alpha:3-3/4; DMM Response Type:True RMS; Calibrated:No; Current Setting AC:1000A; Resistance Measuring Range:400 Ohm to 10 MOhm; Voltage Measuring Range AC:600V RoHS Compliant: NA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL30105 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for AdvancedTCA and H.110
ZL30105_05 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110
ZL30105QDG 制造商:Zarlink Semiconductor Inc 功能描述:CLOCK SYNTHESIZER 64TQFP - Bulk
ZL30105QDG1 制造商:Microsemi Corporation 功能描述:CLOCK SYNTHESIZER 64TQFP - Trays 制造商:Microsemi Corporation 功能描述:IC Pb Free T1/E1 System Synchronizer 制造商:Zarlink Semiconductor Inc 功能描述:CLOCK SYNTHESIZER 64TQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:IC Pb Free T1/E1 System Synchronizer
ZL30106 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH/PDH Network Interface DPLL
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*