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參數(shù)資料
| 型號： | ZL30102QDG1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, LEAD FREE, MS-026ACD, TQFP-64 |
| 文件頁數(shù)： | 22/48頁 |
| 文件大?。?/td> | 944K |
| 代理商： | ZL30102QDG1 |
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ZL30102
Data Sheet
22
Zarlink Semiconductor Inc.
4.4.4 Automatic Mode
The Automatic mode combines the functionality of the Normal mode (automatic Holdover) with automatic reference
switching. The automatic reference switching is described in more detail in section 4.5.2, “Automatic Reference
Switching“.
4.5 Reference Switching
4.5.1 Manual Reference Switching
In the manual modes of operation (MODE_SEL1:0
≠
11) the active reference input (REF0, REF1 or REF2) is
selected by the REF_SEL1 and REF_SEL0 pins as shown in Table 5. When the logic value of the REF_SEL pins is
changed when the DPLL is in Normal mode, the ZL30102 will perform a hitless reference switch.
When the REF_SEL inputs are used in Normal mode to force a change from the currently selected reference to
another reference, the action of the LOCK output will depend on the relative frequency and phase offset of the old
and new references. Where the new reference has enough frequency offset and/or TIE-corrected phase offset to
force the output outside the phase-lock-window, the LOCK output will de-assert, the lock-qualify timer is reset, and
LOCK will stay de-asserted for the full lock-time duration. Where the new reference is close enough in frequency
and TIE-corrected phase for the output to stay within the phase-lock-window, the LOCK output will remain asserted
through the reference-switch process.
Figure 12 - Reference Switching in Normal Mode
REF_SEL1
REF_SEL0
Input Reference Selected
0
0
REF0
0
1
REF1
1
0
REF2
1
1
REF2
Table 5 - Manual Reference Selection
REF1
REF0
REF_SEL
LOCK
Lock Time
Note: LOCK pin behaviour depends on phase and frequency offset of REF1.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL30102 | T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 |
| ZL30102QDG | T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 |
| ZL30105QDG1 | T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110 |
| ZL30105 | Power Clamp On Multimeter; DMM Type:Clamp; No. of Digits/Alpha:3-3/4; DMM Response Type:True RMS; Approval Categories:CAT III 600V; Calibrated:No; Current Measuring Range:0-400.0A; Current Setting AC:400A RoHS Compliant: NA |
| ZL30105QDG | Digital Clamp-On Meter; DMM Type:Clamp; No. of Digits/Alpha:3-3/4; DMM Response Type:True RMS; Calibrated:No; Current Setting AC:1000A; Resistance Measuring Range:400 Ohm to 10 MOhm; Voltage Measuring Range AC:600V RoHS Compliant: NA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30105 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for AdvancedTCA and H.110 |
| ZL30105_05 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110 |
| ZL30105QDG | 制造商:Zarlink Semiconductor Inc 功能描述:CLOCK SYNTHESIZER 64TQFP - Bulk |
| ZL30105QDG1 | 制造商:Microsemi Corporation 功能描述:CLOCK SYNTHESIZER 64TQFP - Trays 制造商:Microsemi Corporation 功能描述:IC Pb Free T1/E1 System Synchronizer 制造商:Zarlink Semiconductor Inc 功能描述:CLOCK SYNTHESIZER 64TQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:IC Pb Free T1/E1 System Synchronizer |
| ZL30106 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH/PDH Network Interface DPLL |
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