參數(shù)資料
型號(hào)： ZL30102QDG1
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP64
封裝： 10 X 10 MM, 1 MM HEIGHT, LEAD FREE, MS-026ACD, TQFP-64
文件頁(yè)數(shù)： 13/48頁(yè)
文件大?。?/td> 944K
代理商： ZL30102QDG1
ZL30102
Data Sheet
13
Zarlink Semiconductor Inc.
Figure 4 - Behaviour of the Dis/Re-qualify Timer
When the incoming signal returns to normal (REF_FAIL=0), the DPLL returns to Normal mode with the output
signal locked to the input signal. Each of the monitors has a built-in hysteresis to prevent flickering of the REF_FAIL
status pin at the threshold boundaries. The precise frequency monitor and the timer do not affect the mode
(Holdover/Normal) of the DPLL.
If the device is set to Automatic mode (MODE_SEL1:0=11), then the state machine does not immediately switch to
another reference. If the single cycle and/or coarse frequency failures persist for more than 2.5 s or the precise
frequency monitor detects a failure, then the state machine will switch to another valid reference if that is available.
If there no other reference available, it stays in Holdover mode.
The precise frequency monitor’s failure thresholds are selected with the OOR_SEL input based on the ZL30102
applications, Table 1. Figure 5 and Figure 6 show the out of range limits for various master clock accuracies. It will
take the precise frequency monitor up to 10 s to qualify or disqualify the input reference.
Figure 5 - DS1 Out-of-Range Thresholds for OOR_SEL=0
2.5 s
10 s
REF0
dis/re-qualify
timer on REF0
SCM or CFM failure
REF_FAIL0
HOLDOVER
REF_OOR0
(internal signal)
REF1
REF0
REF1
REF0
REF_SEL
SCM or CFM failure
C20 Clock Accuracy
0 ppm
+32 ppm
-32 ppm
0
51
83
64
32
32
-32
-96
-75
-50
0
-25
25
75
Frequency offset [ppm]
Out of Range
Out of Range
Out of Range
In Range
In Range
In Range
C20
50
-64
-83
115
96
-32
-51
-115
C20
C20
100
-100
C20: 20 MHz master oscillator clock
相關(guān)PDF資料
PDF描述
ZL30102 T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110
ZL30102QDG T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110
ZL30105QDG1 T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110
ZL30105 Power Clamp On Multimeter; DMM Type:Clamp; No. of Digits/Alpha:3-3/4; DMM Response Type:True RMS; Approval Categories:CAT III 600V; Calibrated:No; Current Measuring Range:0-400.0A; Current Setting AC:400A RoHS Compliant: NA
ZL30105QDG Digital Clamp-On Meter; DMM Type:Clamp; No. of Digits/Alpha:3-3/4; DMM Response Type:True RMS; Calibrated:No; Current Setting AC:1000A; Resistance Measuring Range:400 Ohm to 10 MOhm; Voltage Measuring Range AC:600V RoHS Compliant: NA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL30105 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for AdvancedTCA and H.110
ZL30105_05 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110
ZL30105QDG 制造商:Zarlink Semiconductor Inc 功能描述:CLOCK SYNTHESIZER 64TQFP - Bulk
ZL30105QDG1 制造商:Microsemi Corporation 功能描述:CLOCK SYNTHESIZER 64TQFP - Trays 制造商:Microsemi Corporation 功能描述:IC Pb Free T1/E1 System Synchronizer 制造商:Zarlink Semiconductor Inc 功能描述:CLOCK SYNTHESIZER 64TQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:IC Pb Free T1/E1 System Synchronizer
ZL30106 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH/PDH Network Interface DPLL
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