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參數(shù)資料
| 型號： | ZL30102QDG1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, LEAD FREE, MS-026ACD, TQFP-64 |
| 文件頁數(shù)： | 10/48頁 |
| 文件大?。?/td> | 944K |
| 代理商： | ZL30102QDG1 |
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ZL30102
Data Sheet
10
Zarlink Semiconductor Inc.
43
C8/C32o
Clock 8.192 MHz or 32.768 MHz (Output).
This output is used for ST-BUS and GCI
operation at 8.192 Mb/s or for operation with a 32.768 MHz clock. The output frequency
is selected via the OUT_SEL pin, see Table 3 on page 19.
In C8 mode, this clock output pad uses an included Schmitt input as a PLL feedback
path; proper transmission-line termination should be applied to maintain reflections below
Schmitt trigger levels.
44
AV
DD
AV
DD
C2o
Positive Analog Supply Voltage.
+3.3 V
DC
nominal
Positive Analog Supply Voltage.
+3.3 V
DC
nominal
Clock 2.048 MHz (Output).
This output is used for standard E1 interface timing and for
ST-BUS operation at 2.048 Mbit/s.
45
46
This clock output pad includes a Schmitt input which serves as a PLL feedback path;
proper transmission-line termination should be applied to maintain reflections below
Schmitt trigger levels.
47
C16o
Clock 16.384 MHz (Output).
This output is used for ST-BUS operation with a
16.384 MHz clock.
This clock output pad includes a Schmitt input which serves as a PLL feedback path;
proper transmission-line termination should be applied to maintain reflections below
Schmitt trigger levels.
48
F8/F32o
Frame Pulse (Output).
This is an 8 kHz 122 ns active high framing pulse or it is an 8 kHz
31 ns active high framing pulse, which marks the beginning of a frame. The pulse width is
selected via the OUT_SEL pin, see Table 3 on page 19.
49
F4/F65o
Frame Pulse ST-BUS 2.048 Mbit/s or ST-BUS at 65.536 MHz clock (Output).
This
output is an 8 kHz 244 ns active low framing pulse which marks the beginning of an ST-
BUS frame. This is typically used for ST-BUS operation at 2.048 Mbit/s and 4.096 Mbit/s.
Or this output is an 8 kHz 15 ns active low framing pulse, typically used for ST-BUS
operation with a clock rate of 65.536 MHz. The pulse width is selected via the OUT_SEL
pin, see Table 3 on page 19.
50
F16o
Frame Pulse ST-BUS 8.192 Mbit/s (Output).
This is an 8 kHz 61 ns active low framing
pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS
operation at 8.192 Mbit/s.
51
AGND
Analog Ground.
0 V
52
IC
Internal Connection.
Connect this pin to ground.
53
REF_SEL0
Reference Select 0 (Input/Output).
In the manual mode of operation, REF_SEL0 is an
input. As an input REF_SEL0 combined with REF_SEL1 selects the reference input that
is used for synchronization, see Table 6 on page 23.
In the Automatic mode of operation, REFSEL0 is an output indicating which of the input
references is the being selected. This pin is internally pulled down to GND.
54
REF_SEL1
Reference Select 1 (Input/Output)
. See REF_SEL0 pin description.
55
REF0
Reference (Input).
This is one of three (REF0, REF1 and REF2) input reference sources
used for synchronization. One of five possible frequencies may be used: 8 kHz,
1.544 MHz, 2.048 MHz, 8.192 MHz or 16.384 MHz. This pin is internally pulled down to
GND.
56
REF1
Reference (Input).
See REF0 pin description.
57
REF2
Reference (Input).
See REF0 pin description.
Pin #
Name
Description
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|---|---|
| ZL30105 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for AdvancedTCA and H.110 |
| ZL30105_05 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110 |
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| ZL30106 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH/PDH Network Interface DPLL |
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