參數(shù)資料
型號： XR88C681CJTR-F
廠商： Exar Corporation
文件頁數(shù)： 9/101頁
文件大?。?/td> 0K
描述： IC UART CMOS DUAL 44PLCC
標準包裝： 500
特點： *
通道數(shù)： 2，DUART
FIFO's： 1 字節(jié)，3 字節(jié)
電源電壓： 4.75 V ~ 5.25 V
帶并行端口： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應商設備封裝： 44-PLCC（16.59x16.59）
包裝： 帶卷 (TR)
其它名稱： XR88C681CJTR-F-ND
XR88C681
15
Rev. 2.11
Address (Hex)
Read Mode Registers
Write Mode Registers
Register Name
Symbol
Register Name
Symbol
00
Mode Register,
Channel A
MR1A, MR2A
Mode Register,
Channel A
MR1A, MR2A
01
Status Register,
Channel A
SRA
Clock Select Register,
Channel A
CSRA
02
Masked Interrupt
Status Register
MISR
Command Register A
CRA
03
Rx Holding Register,
Channel A
RHRA
Tx Holding Register,
Channel A
THRA
04
Input Port Change
Register
IPCR
Auxiliary Control
Register
ACR
05
Interrupt Status
Register
ISR
Interrupt Mask Register
IMR
06
Counter/Timer Upper
Byte Register
CTU
Counter/Timer
Upper Byte Register
CTU
07
Counter/Timer Lower
Byte Register
CTL
Counter/Timer Lower
Byte Register
CTL
08
Mode Register,
Channel B
MR1B, MR2B
Mode Register,
Channel B
MR1B, MR2B
09
Status Register,
Channel B
SRB
Clock Select Register,
Channel B
CSRB
0A
RESERVED
Command Register,
Channel B
CRB
0B
Rx Holding Register,
Channel B
RHRB
Tx Holding Register,
Channel B
THRB
0C
Interrupt Vector
Register
IVR
Interrupt Vector
Register
IVR
0D
Input Port
IP
Output Port
Configuration Register
(OP0 - OP7)
OPCR
0E
Start Counter/Timer
Command
SCC
Set Output Port Bits
Command
SOPBC
0F
Stop Counter/Timer
Command
STC
Clear Output Port Bits
Command
COPBC
Table 1. DUART Port and Register Addressing
Note:
The shaded blocks are not Read/Write registers but are rather “Address-Triggered” Commands.
Table 1 indicates that each channel is equipped with two Mode Registers. Associated with each of these Mode Register
pairs is a “Mode Register” pointer or MR pointer. Upon chip/system power up or RESET each MR pointer is “pointing to”
the channel MR1n register. (
Please note that the suffix “n” is used at the end of many of the DUART registers symbols in
order to refer, generically, to either channels A or B). However, the contents of the MR pointer will shift from the address
of the MR1n register to that of the MR2n register, immediately following any Read or Write access to the MR1n register.
The MR pointer will continue to “point to” the MR2n register until a hardware reset occurs or until a “RESET MR
POINTER” command has been invoked. The “RESET MR POINTER” command can be issued by writing the
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