參數(shù)資料
型號(hào): XR16C2550IMTR-F
廠商: Exar Corporation
文件頁(yè)數(shù): 1/37頁(yè)
文件大?。?/td> 0K
描述: IC UART FIFO 16B DUAL 48TQFP
標(biāo)準(zhǔn)包裝: 1,500
特點(diǎn): *
通道數(shù): 2,DUART
FIFO's: 16 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.97 V ~ 5.5 V
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 帶卷 (TR)
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
FEBRUARY 2007
REV. 1.0.2
GENERAL DESCRIPTION
The
XR16C2550
(2550)
is
a
dual
universal
asynchronous receiver and transmitter (UART). The
XR16C2550 is an improved version of the PC16550
UART with higher operating speed and faster access
times. The 2550 provides enhanced UART functions
with 16 byte FIFO’s, a modem control interface, and
data rates up to 4 Mbps. Onboard status registers
provide
the
user
with
error
indications
and
operational status. System interrupts and modem
control features may be tailored by external software
to meet specific user requirements. Independent
programmable baud rate generators are provided to
select transmit and receive clock rates from 50 bps to
4 Mbps. The Baud Rate Generator can be configured
for either crystal or external clock input. An internal
loopback capability allows onboard diagnostics. The
2550 is available in a 44-pin PLCC and 48-pin TQFP
packages. The 2550 is fabricated in an advanced
CMOS process capable of operating from 2.97 volt to
5.5 volt power supply.
APPLICATIONS
Portable Appliances
Telecommunication Network Routers
Ethernet Network Routers
Cellular Data Devices
Factory Automation and Process Controls
FEATURES
2.97 Volt to 5.5 Volt Operation
5 Volt Tolerant Inputs
Pin-to-pin compatible to Exar’s ST16C2450,
XR16L2550 and XR16L2750
Pin-to-pin compatible to TI’s TL16C752B on the 48-
TQFP package
Pin alike XR16C2850 48-TQFP package but
without CLK8/16, CLKSEL and HDCNTL inputs
2 independent UART channels
Up to 4 Mbps with external clock of 64 MHz
Up to 1.5 Mbps data rate with a 24 MHz crystal
frequency
16 byte Transmit FIFO to reduce the bandwidth
requirement of the external CPU
16 byte Receive FIFO with error tags to reduce
the bandwidth requirement of the external CPU
4 selectable Receive FIFO interrupt trigger
levels
Modem control signals (CTS#, RTS#, DSR#,
DTR#, RI#, CD#)
Programmable character lengths (5, 6, 7, 8)
with even, odd, or no parity
Crystal oscillator or external clock input
48-TQFP and 44-PLCC packages
FIGURE 1. XR16C2550 BLOCK DIAGRAM
XTAL1
XTAL2
Crystal Osc / Buffer
TXA , RXA, DTRA#,
DSRA#, RTSA#,
DTSA#, CDA#, RIA#,
OP2A#
8- bit Data
Bus
Interface
UART Channel A
16 Byte TX FIFO
16 Byte RX FIFO
BRG
TX & RX
UART
Regs
2.97 V to5.5V
GND
TXB, RXB, DTRB#,
DSRB#, RTSB#,
CTSB#, CDB#, RIB#,
OP2B#
UART Channel B
( same as Channel A )
A2:A0
D7:D0
CSA#
CSB#
INTA
INTB
IOW#
IOR#
Reset
TXRDYA#
TXRDYB#
RXRDYA#
RDRXYB#
*All inputs are 5V tolerant
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