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參數(shù)資料
| 型號： | XC4028XLA |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Field Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
| 中文描述： | 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 72K |
| 代理商： | XC4028XLA |
R
DS004 (v. 1.3) October 4, 1999 - Product Specification
6-177
XC4000XLA/XV FIeld Programmable Gate Arrays
6
CLB Dual Port RAM Synchronous (Edge-Triggered) Write Operation Guidelines
CLB RAM Synchronous (Edge-Triggered) Write Timing Waveforms
Dual Port RAM
Speed Grade
-09
-08
-07
Units
Size
Symbol
Min
Max
Min
Max
Min
Max
Address write cycle time (clock K period)
16x1
T
WCDS
T
WPDS
T
ASDS
T
AHDS
T
DSDS
T
DHDS
T
WSDS
T
WHDS
T
WODS
6.7
5.9
5.3
ns
Clock K pulse width (active edge)
16x1
3.4
3.0
2.7
ns
Address setup time before clock K
16x1
1.5
1.3
1.2
ns
Address hold time after clock K
16x1
0.0
0.0
0.0
ns
DIN setup time before clock K
16x1
1.7
1.6
1.4
ns
DIN hold time after clock K
16x1
0.0
0.0
0.0
ns
WE setup time before clock K
16x1
1.4
1.3
1.1
ns
WE hold time after clock K
16x1
0.0
0.0
0.0
ns
Data valid after clock K
16x1
5.7
5.1
4.6
ns
Note: Timing for 16x1 option is identical to 16x2 RAM.
Preliminary
X6461
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT
OLD
NEW
T
DSS
T
DHS
T
ASS
T
AHS
T
WSS
T
WPS
T
WHS
T
WOS
T
ILO
T
ILO
Dual Port RAM
Single Port RAM
WCLK (K)
WE
ADDRESS
DATA IN
T
DSDS
T
DHDS
T
ASDS
T
AHDS
T
WSDS
T
WPDS
T
WHDS
X6474
DATA OUT
OLD
NEW
T
WODS
T
ILO
T
ILO
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