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參數(shù)資料
| 型號： | XC4028XLA |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Field Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
| 中文描述： | 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 6/16頁 |
| 文件大小： | 72K |
| 代理商： | XC4028XLA |
R
XC4000XLA/XV FIeld Programmable Gate Arrays
6-176
DS004 (v. 1.3) October 4, 1999 - Product Specification
CLB SIngle Port RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XC4000XLA devices and are expressed in nanoseconds unless otherwise noted.
Single Port RAM
Speed Grade
-09
-08
-07
Units
Size
Symbol
Min
Max
Min
Max
Min
Max
Write Operation
Address write cycle time (clock K period)
16x2
32x1
T
WCS
T
WCTS
T
WPS
T
WPTS
T
ASS
T
ASTS
T
AHS
T
AHTS
T
DSS
T
DSTS
T
DHS
T
DHTS
T
WSS
T
WSTS
T
WHS
T
WHTS
T
WOS
T
WOTS
6.7
6.7
5.9
5.9
5.3
5.3
ns
ns
Clock K pulse width (active edge)
16x2
32x1
3.4
3.4
3.0
3.0
2.7
2.7
ns
ns
Address setup time before clock K
16x2
32x1
1.5
1.5
1.3
1.3
1.2
1.2
ns
ns
Address hold time after clock K
16x2
32x1
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
DIN setup time before clock K
16x2
32x1
1.5
1.8
1.3
1.6
1.2
1.5
ns
ns
DIN hold time after clock K
16x2
32x1
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
WE setup time before clock K
16x2
32x1
1.4
1.3
1.3
1.2
1.1
1.1
ns
ns
WE hold time after clock K
16x2
32x1
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
Data valid after clock K
16x2
32x1
5.0
5.8
4.4
5.2
4.2
4.7
ns
ns
Read Operation
Address read cycle time
16x2
32x1
T
RC
T
RCT
T
ILO
T
IHO
T
ICK
T
IHCK
2.6
3.8
2.6
3.8
2.6
3.8
ns
ns
Data Valid after address change (no Write En-
able)
16x2
32x1
1.1
1.9
1.0
1.7
0.9
1.5
ns
ns
Address setup time before clock K
16x2
32x1
0.7
1.4
0.7
1.3
0.6
1.2
ns
ns
Preliminary
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