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參數(shù)資料
| 型號： | XC4028XLA |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Field Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
| 中文描述： | 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 13/16頁 |
| 文件大小： | 72K |
| 代理商： | XC4028XLA |
R
DS004 (v. 1.3) October 4, 1999 - Product Specification
6-183
XC4000XLA/XV FIeld Programmable Gate Arrays
6
BUFGE #s 3, 4, 7, and 8 Global Early Clock, Set-up and Hold for IFF and FCL
Speed Grade
Description
Input Setup and Hold Time Relative to Global Clock Input Signal
No Delay
Global Early Clock and IFF
Global Early Clock and FCL
-09
Min
-08
Min
-07
Min
Units
Symbol
Device
XC4013XLA
XC4020XLA
XC4028XLA
XC4036XLA
XC4044XLA
XC4052XLA
XC4062XLA
XC4085XLA
XC4013XLA
XC4020XLA
XC4028XLA
XC4036XLA
XC4044XLA
XC4052XLA
XC4062XLA
XC4085XLA
XC4013XLA
XC4020XLA
XC4028XLA
XC4036XLA
XC4044XLA
XC4052XLA
XC4062XLA
XC4085XLA
0.8 / 3.2
0.8 / 3.4
0.8 / 3.5
0.8 / 3.6
0.8 / 3.8
0.8 / 4.0
0.8 / 4.2
0.8 / 4.6
4.4 / 0.0
4.6 / 0.1
4.7 / 0.1
4.8 / 0.2
5.2 / 0.3
5.6 / 0.3
6.0 / 0.4
6.3 / 0.5
4.4 / 0.0
4.7 / 0.0
4.9 / 0.0
5.1 / 0.0
5.6 / 0.0
6.0 / 0.0
6.5 / 0.0
6.8 / 0.0
0.6 / 2.6
0.6 / 2.8
0.6 / 3.0
0.6 / 3.1
0.6 / 3.3
0.6 / 3.5
0.6 / 3.7
0.6 / 4.0
4.0 / 0.0
4.2 / 0.1
4.4 / 0.1
4.5 / 0.2
4.8 / 0.3
5.1 / 0.3
5.4 / 0.4
5.7 / 0.5
4.0 / 0.0
4.3 / 0.0
4.5 / 0.0
4.7 / 0.0
5.1 / 0.0
5.5 / 0.0
5.9 / 0.0
6.2 / 0.0
Preliminary
0.4 / 2.0
0.4 / 2.2
0.4 / 2.4
0.4 / 2.6
0.4 / 2.8
0.4 / 3.0
0.4 / 3.2
0.4 / 3.4
3.6 / 0.0
3.8 / 0.0
4.1 / 0.0
4.2 / 0.0
4.4 / 0.0
4.6 / 0.0
4.8 / 0.0
5.0 / 0.0
3.6 / 0.0
3.8 / 0.0
4.1 / 0.0
4.2 / 0.0
4.6 / 0.0
4.9 / 0.0
5.2 / 0.0
5.6 / 0.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
PSEN
/T
PHEN
T
PFSEN
/T
PFHEN
Partial Delay
Global Early Clock and IFF
Global Early Clock and FCL
T
PSEP
/T
PHEP
T
PFSEP
/T
PFHEP
Full Delay
Global Early Clock and IFF
T
PSED
/T
PHED
IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch
Note:
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is
measured relative to the Global Clock input signal using the furthest distance and a reference load of one clock pin per two
IOBs. Use the static timing analyzer (TRCE) to determine the setup and hold times under given design conditions.
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