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參數(shù)資料
| 型號： | XC4028XLA |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Field Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
| 中文描述： | 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 72K |
| 代理商： | XC4028XLA |
R
DS004 (v. 1.3) October 4, 1999 - Product Specification
6-185
XC4000XLA/XV FIeld Programmable Gate Arrays
6
XLA IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless
otherwise noted. Values are expressed in nanoseconds unless otherwise noted.
Speed Grade
-09
-08
-07
Units
Description
Symbol
Device
Min
Max
Min
Max
Min
Max
Clocks
Clock High
T
CH
T
CL
All devices
2.2
1.9
1.7
ns
Clock Low
All devices
2.2
1.9
1.7
ns
Propagation Delays
Clock (OK) to Pad
T
OKPOF
T
OPF
T
TSHZ
T
TSONF
T
OKSHZ
T
OKSONF
T
OFPF
T
OKFPF
All devices
3.2
2.9
2.6
ns
Output (O) to Pad
All devices
2.6
2.4
2.1
ns
3-state to Pad hi-Z (slew-rate independent)
All devices
2.7
2.4
2.2
ns
3-state to Pad active and valid
All devices
2.8
2.5
2.3
ns
Clock to Pad hi-Z
All devices
3.5
3.1
2.8
ns
Clock to Pad active and valid
All devices
3.6
3.2
2.9
ns
Output (O) to Pad via Fast Output MUX
All devices
3.6
3.2
2.9
ns
Select (OK) to Pad via Fast MUX
All devices
3.3
3.0
2.6
ns
Setup and Hold Times
Output (O) to clock (OK) setup time
T
OOK
T
OKO
T
ECOK
T
OKEC
All devices
0.3
0.3
0.3
ns
Output (O) to clock (OK) hold time
All devices
0.0
0.0
0.0
ns
Clock Enable (EC) to clock (OK) setup time
All devices
0.0
0.0
0.0
ns
Clock Enable (EC) to clock (OK) hold time
All devices
0.0
0.0
0.0
ns
Global Set/Reset
Minimum GSR pulse width
T
MRW
T
RPO*
12.8
11.4
10.2
ns
Delay from GSR input to any Pad
XC4013XLA
14.4
12.8
11.5
ns
XC4020XLA
16.3
14.5
13.0
ns
XC4028XLA
17.3
15.4
13.8
ns
XC4036XLA
19.1
17.1
15.3
ns
XC4044XLA
21.0
18.8
16.8
ns
XC4052XLA
22.5
20.1
17.9
ns
XC4062XLA
23.9
21.3
19.0
ns
XC4085XLA
27.7
24.7
22.1
ns
Slew Rate Adjustment
For output SLOW option add
T
SLOW
1.7
1.6
1.4
ns
* Indicates Minimum Amount of Time to Assure Valid Data
Preliminary
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