- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374999 > XC4028XLA (Xilinx, Inc.) Field Programmable Gate Arrays(現(xiàn)場可編程門陣列) PDF資料下載
參數(shù)資料
| 型號： | XC4028XLA |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Field Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
| 中文描述： | 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 72K |
| 代理商： | XC4028XLA |
R
XC4000XLA/XV FIeld Programmable Gate Arrays
6-182
DS004 (v. 1.3) October 4, 1999 - Product Specification
BUFGE #s 1, 2, 5, and 6 Global Early Clock, Set-up and Hold for IFF and FCL
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation net list. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted.
Speed Grade
Description
Input Setup and Hold Time Relative to Global Clock Input Signal
No Delay
Global Early Clock and IFF
Global Early Clock and FCL
-09
Min
-08
Min
-07
Min
Units
Symbol
Device
XC4013XLA
XC4020XLA
XC4028XLA
XC4036XLA
XC4044XLA
XC4052XLA
XC4062XLA
XC4085XLA
XC4013XLA
XC4020XLA
XC4028XLA
XC4036XLA
XC4044XLA
XC4052XLA
XC4062XLA
XC4085XLA
XC4013XLA
XC4020XLA
XC4028XLA
XC4036XLA
XC4044XLA
XC4052XLA
XC4062XLA
XC4085XLA
1.0 / 3.2
1.0 / 3.4
1.0 / 3.5
1.0 / 3.6
1.0 / 3.8
1.0 / 4.0
1.0 / 4.2
1.0 / 4.6
4.6 / 0.0
4.8 / 0.1
4.9 / 0.1
5.0 / 0.2
5.5 / 0.3
5.8 / 0.3
6.2 / 0.4
6.5 / 0.5
4.6 / 0.0
4.9 / 0.0
5.1 / 0.0
5.3 / 0.0
5.8 / 0.0
6.2 / 0.0
6.7 / 0.0
7.0 / 0.0
0.8 / 2.6
0.8 / 2.8
0.8 / 3.0
0.8 / 3.1
0.8 / 3.3
0.8 / 3.5
0.8 / 3.7
0.8 / 4.0
4.2 / 0.0
4.4 / 0.1
4.6 / 0.1
4.7 / 0.1
5.1 / 0.2
5.3 / 0.2
5.6 / 0.2
5.9 / 0.3
4.2 / 0.0
4.5 / 0.0
4.7 / 0.0
4.9 / 0.0
5.3 / 0.0
5.7 / 0.0
6.1 / 0.0
6.4 / 0.0
Preliminary
0.5 / 1.8
0.5 / 2.0
0.5 / 2.2
0.5 / 2.4
0.5 / 2.6
0.5 / 2.8
0.5 / 3.0
0.5 / 3.2
3.9 / 0.0
4.1 / 0.0
4.4 / 0.0
4.5 / 0.0
4.8 / 0.0
5.0 / 0.0
5.2 / 0.0
5.4 / 0.0
3.9 / 0.0
4.1 / 0.0
4.4 / 0.0
4.5 / 0.0
5.0 / 0.0
5.3 / 0.0
5.6 / 0.0
6.0 / 0.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
PSEN
/T
PHEN
T
PFSEN
/T
PFHEN
Partial Delay
Global Early Clock and IFF
Global Early Clock and FCL
T
PSEP
/T
PHEP
T
PFSEP
/T
PFHEP
Full Delay
Global Early Clock and IFF
T
PSED
/T
PHED
IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch
Note:
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is
measured relative to the Global Clock input signal using the furthest distance and a reference load of one clock pin per two
IOBs. Use the static timing analyzer (TRCE) to determine the setup and hold times under given design conditions.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC4044XLA-08HQ240I | XC4000XLA/XV Field Programmable Gate Arrays |
| XC4044XL | XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4044XLA | XC4000XLA/XV Field Programmable Gate Arrays |
| XC40250XV | XC4000XLA/XV Field Programmable Gate Arrays |
| XC40150XV | XC4000XLA/XV Field Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC4028XLA-07HQ240C | 制造商:Xilinx 功能描述: |
| XC4028XLA-08BG352C0314 | 制造商:Xilinx 功能描述: |
| XC4028XLA-08BG352C0716 | 制造商:Xilinx 功能描述: |
| XC4028XLA08HQ208C | 制造商:Xilinx 功能描述: |
| XC4028XLA-08HQ208C | 制造商:Xilinx 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。