參數(shù)資料
型號(hào)： XC4028XLA
廠商： Xilinx, Inc.
英文描述： Field Programmable Gate Arrays(現(xiàn)場(chǎng)可編程門陣列)
中文描述： 現(xiàn)場(chǎng)可編程門陣列（現(xiàn)場(chǎng)可編程門陣列）
文件頁(yè)數(shù)： 3/16頁(yè)
文件大?。?/td> 72K
代理商： XC4028XLA
R
DS004 (v. 1.3) October 4, 1999 - Product Specification
6-173
XC4000XLA/XV FIeld Programmable Gate Arrays
6
XC4000 XLA Switching Characteristics
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven
from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting
the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System)
and back-annotated to the simulation net list. These path delays, provided as a guideline, have been extracted from the
static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction
temperature. Values apply to all XC4000XLA devices and expressed in nanoseconds unless otherwise noted.
Delay Via Global Low Skew Clock Buffer to Clock
Delay Via FastCLK Buffer to IOB Clock
Speed Grade
Symbol
T
GLS
All
Min
0.7
0.7
0.8
0.8
0.9
1.0
1.1
1.2
-09
Max
2.4
2.6
2.9
3.2
3.6
3.9
4.2
5.0
Preliminary
-08
Max
2.1
2.3
2.6
2.8
3.1
3.4
3.7
4.4
-07
Max
1.9
2.1
2.3
2.5
2.8
3.1
3.3
3.9
Units
Description
Device
XC4013XLA
XC4020XLA
XC4028XLA
XC4036XLA
XC4044XLA
XC4052XLA
XC4062XLA
XC4085XLA
Delay from pad through Global Low Skew (GLS) clock
buffer to any clock input, K.
ns
ns
ns
ns
ns
ns
ns
ns
Speed Grade
Symbol
T
FCLK
All
Min
0.4
0.5
0.5
0.5
0.5
0.6
0.6
0.6
-09
Max
1.5
1.5
1.6
1.7
1.8
1.9
2.0
2.3
Preliminary
-08
Max
1.3
1.3
1.4
1.5
1.6
1.7
1.8
2.0
-07
Max
1.1
1.2
1.3
1.4
1.4
1.5
1.6
1.8
Units
Description
Device
XC4013XLA
XC4020XLA
XC4028XLA
XC4036XLA
XC4044XLA
XC4052XLA
XC4062XLA
XC4085XLA
Delay from pad through FastCLK buffer to any IOB
clock input.
ns
ns
ns
ns
ns
ns
ns
ns
Note: Values in
bold face
are preliminary, all other values are advance.
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