參數(shù)資料
型號(hào)： XC4005-36XL
廠商： Xilinx, Inc.
英文描述： XC4000XL Electrical Specifications
中文描述： XC4000XL電氣規(guī)格
文件頁(yè)數(shù)： 9/16頁(yè)
文件大小： 76K
代理商： XC4005-36XL
R
DS005 (v. 1.8 October 18, 1999 - Product Specification
6-81
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Output Flip-Flop, Clock to Out, BUFGE #s 1, 2, 5, and 6
Output Flip-Flop, Clock to Out, BUFGE #s 3, 4, 7, and 8
Speed Grade
Description
Global Early Clock to Output using
Output Flip Flop. Values are for BUF-
GE #s 1, 2, 5, and 6.
All
Min
1.0
1.2
1.2
1.3
1.3
1.2
1.2
1.1
1.2
1.2
1.3
-3
-2
-1
-09
Max
4.8
5.2
5.3
5.3
5.6
5.6
5.8
6.0
6.6
7.0
7.9
-08
Max
Units
Symbol
T
ICKEOF
Device
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
Max
6.6
6.9
7.2
7.4
7.6
7.8
8.1
8.5
9.0
9.9
10.8
Max
5.7
6.1
6.2
6.4
6.5
6.7
7.0
7.3
7.8
8.6
9.4
Max
5.1
5.5
5.5
5.6
5.9
5.9
6.1
6.4
6.8
7.5
8.5
4.8
5.2
6.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is
measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin
clock-to-out delay for clocked outputs for FAST mode configurations.
Output timing is measured at ~50% V
CC
threshold with 50 pF external capacitive load. For different loads, see Figure 1.
Speed Grade
Description
Global Early Clock to Output using
Output Flip Flop. Values are for BUF-
GE #s 3, 4, 7, and 8.
All
Min
1.3
1.5
1.6
1.6
1.7
1.7
1.8
1.9
2.0
2.0
2.2
-3
-2
-1
-09
Max
5.3
6.1
6.3
6.4
6.8
6.9
7.2
7.3
7.9
8.1
8.8
-08
Max
Units
Symbol
T
ICKEOF
Device
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
Max
7.8
8.1
8.5
8.8
9.1
9.4
9.7
10.1
10.5
10.9
11.8
Max
6.8
7.1
7.4
7.6
7.9
8.2
8.5
8.8
9.1
9.5
10.3
Max
5.9
6.5
6.6
6.7
7.2
7.2
7.5
7.8
8.1
8.6
9.3
5.7
6.4
7.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is
measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin
clock-to-out delay for clocked outputs for FAST mode configurations.
Output timing is measured at ~50% V
CC
threshold with 50 pF external capacitive load. For different loads, see Figure 1.
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