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參數(shù)資料
| 型號： | XC4005-36XL |
| 廠商： | Xilinx, Inc. |
| 英文描述： | XC4000XL Electrical Specifications |
| 中文描述： | XC4000XL電氣規(guī)格 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大小： | 76K |
| 代理商： | XC4005-36XL |
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-80
DS005 (v. 1.8 October 18, 1999 - Product Specification
XC4000XL Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted.
Output Flip-Flop, Clock to Out
Capacitive Load Factor
Figure 60
shows the relationship between I/O output delay
and load capacitance. It allows a user to adjust the speci-
fied output delay if the load capacitance is different than
50 pF. For example, if the actual load capacitance is
120 pF, add 2.5 ns to the specified delay. If the load capac-
itance is 20 pF, subtract 0.8 ns from the specified output
delay.
Figure 60
is usable over the specified operating conditions
of voltage and temperature and is independent of the out-
put slew rate control.
Figure 60: Delay Factor at Various Capacitive Loads
Speed Grade
Description
Global Low Skew Clock to Output us-
ing Output Flip Flop
All
Min
1.2
1.3
1.4
1.5
1.6
1.8
2.0
2.1
2.2
2.3
2.5
0.5
-3
-2
-1
-09
Max
5.1
5.4
5.8
6.1
6.4
6.7
7.0
7.4
7.9
8.1
9.0
1.7
-08
Max
Units
Symbol
T
ICKOF
Device
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
All Devices
Max
7.1
7.7
8.2
8.6
9.0
9.4
9.8
10.3
10.7
11.3
12.2
3.0
Max
6.1
6.6
7.1
7.4
7.8
8.1
8.5
8.9
9.3
9.7
10.5
2.5
Max
5.4
5.8
6.2
6.5
6.8
7.1
7.4
7.8
8.3
8.5
9.5
2.0
5.6
6.4
7.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
For output SLOW option add
T
SLOW
1.6
Notes:
Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is
measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin
clock-to-out delay for clocked outputs for FAST mode configurations.
Output timing is measured at ~50% V
CC
threshold with 50 pF external capacitive load. For different loads, see Figure 1.
X8257
-2
0
20
40
Capacitance (pF)
60
80
D
100
120
140
-1
0
1
2
3
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