參數(shù)資料
型號： XC4005-36XL
廠商： Xilinx, Inc.
英文描述： XC4000XL Electrical Specifications
中文描述： XC4000XL電氣規(guī)格
文件頁數(shù)： 13/16頁
文件大小： 76K
代理商： XC4005-36XL
R
DS005 (v. 1.8 October 18, 1999 - Product Specification
6-85
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000XL IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature)
.
6
Speed Grade
Symbol
-3
Min
-2
Min
-1
Min
-09
Min
-08
Min
Units
Description
Device
Clocks
Clock Enable (EC) to Clock (IK)
Delay from FCL enable (OK) active edge to
IFF clock (IK) active edge
T
ECIK
T
OKIK
All devices
XC4002XL
XC4013, 36, 62XL
Balance of Family
0.1
3.0
2.2
2.2
0.1
2.7
1.9
1.9
0.1
2.3
1.6
1.6
0.1
2.3
1.6
1.6
0.1
ns
ns
ns
ns
1.6
Setup Times
Pad to Clock (IK), no delay
T
PICK
XC4002XL
XC4013, 36, 62XL
Balance of Family
XC4002XL
XC4013, 36, 62XL
Balance of Family
XC4013, 36, 62XL
Balance of Family
2.6
1.7
1.7
3.2
2.3
2.3
1.2
1.2
2.3
1.5
1.5
2.9
2.0
2.0
1.0
1.0
2.0
1.3
1.3
2.5
1.8
1.8
0.9
0.9
2.0
1.3
1.3
2.4
1.7
1.7
0.9
0.9
1.2
ns
ns
ns
ns
ns
ns
ns
ns
Pad to Clock (IK), via transparent Fast Cap-
ture Latch, no delay
T
PICKF
1.6
Pad to Fast Capture Latch Enable (OK), no
delay
Hold Times
All Hold Times
Global Set/Reset
Minimum GSR Pulse Width
Global Set/Reset
Delay from GSR input to any Q
T
POCK
0.9
All Devices
0
0
0
0
0
T
MRW
All devices
19.8
Max
9.8
11.3
13.9
15.9
18.6
20.5
22.5
25.1
27.2
29.1
34.4
17.3
Max
8.5
9.8
12.1
13.8
16.1
17.9
19.6
21.9
23.6
25.3
29.9
15.0
Max
7.4
8.5
10.5
12.0
14.0
15.5
17.0
19.0
20.5
22.0
26.0
14.0
Max
7.0
8.1
10.0
11.4
13.3
14.3
16.2
18.1
19.5
20.9
24.7
14.0
Max
ns
T
RRI*
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
10.9
16.2
20.4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Propagation Delays
Pad to I1, I2
Pad to I1, I2 via transparent input latch,
no delay
T
PID
T
PLI
All devices
XC4002XL
XC4013, 36, 62XL
Balance of Family
X4002XL
XC4013, 36, 62XL
Balance of Family
All devices
All devices
XC4002XL
XC4013, 36, 62XL
Balance of Family
1.6
4.7
3.1
3.1
5.4
3.7
3.7
1.7
1.8
5.2
3.6
3.6
1.4
4.2
2.7
2.7
4.7
3.3
3.3
1.5
1.6
4.6
3.1
3.1
1.2
3.6
2.4
2.4
4.1
2.8
2.8
1.3
1.4
4.0
2.7
2.7
1.1
3.5
2.2
2.2
3.9
2.7
2.7
1.2
1.3
3.8
2.6
2.6
1.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.1
Pad to I1, I2 via transparent FCL and in-
put latch, no delay
T
PFLI
2.5
Clock (IK) to I1, I2 (flip-flop)
Clock (IK) to I1, I2 (latch enable, active
Low)
FCL Enable (OK) active edge to I1, I2
(via transparent standard input latch)
IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch
* Indicates Minimum Amount of Time to Assure Valid Data.
T
IKRI
T
IKLI
T
OKLI
1.2
1.3
2.5
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