參數(shù)資料
型號(hào)： XC4005-36XL
廠商： Xilinx, Inc.
英文描述： XC4000XL Electrical Specifications
中文描述： XC4000XL電氣規(guī)格
文件頁(yè)數(shù)： 6/16頁(yè)
文件大?。?/td> 76K
代理商： XC4005-36XL
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-78
DS005 (v. 1.8 October 18, 1999 - Product Specification
CLB Single-Port RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XC4000XL devices and are expressed in nanoseconds unless otherwise noted.
Single Port RAM
Speed Grade
-3
-2
-1
-09
-08
Size
Symbol Min
Max
Min
Max
Min
Max
Min Max Min Max
Write Operation
Address write cycle time (clock K period)
16x2
32x1
T
WCS
T
WCTS
T
WPS
T
WPTS
T
ASS
T
ASTS
T
AHS
T
AHTS
T
DSS
T
DSTS
T
DHS
T
DHTS
T
WSS
T
WSTS
T
WHS
T
WHTS
T
WOS
T
WOTS
9.0
9.0
8.4
8.4
7.7
7.7
7.4
7.4
7.4
7.4
Clock K pulse width (active edge)
16x2
32x1
4.5
4.5
4.2
4.2
3.9
3.9
3.7
3.7
3.7
3.7
Address setup time before clock K
16x2
32x1
2.2
2.2
2.0
2.0
1.7
1.7
1.7
1.7
1.6
1.7
Address hold time after clock K
16x2
32x1
0
0
0
0
0
0
0
0
0
0
DIN setup time before clock K
16x2
32x1
2.0
2.5
1.9
2.3
1.7
2.1
1.7
2.1
1.7
2.1
DIN hold time after clock K
16x2
32x1
0
0
0
0
0
0
0
0
0
0
WE setup time before clock K
16x2
32x1
2.0
1.8
1.8
1.7
1.6
1.5
1.6
1.5
1.6
1.5
WE hold time after clock K
16x2
32x1
0
0
0
0
0
0
0
0
0
0
Data valid after clock K
16x2
32x1
6.8
8.1
6.3
7.5
5.8
6.9
5.8
6.7
5.7
6.7
Read Operation
Address read cycle time
16x2
32x1
T
RC
T
RCT
T
ILO
T
IHO
T
ICK
T
IHCK
4.5
6.5
3.1
5.5
2.6
3.8
2.6
3.8
2.6
3.8
Data Valid after address change (no
Write Enable)
16x2
32x1
1.6
2.7
1.5
2.4
1.3
2.2
1.2
2.0
1.1
1.9
Address setup time before clock K
16x2
32x1
1.1
2.2
1.0
1.9
0.9
1.7
0.8
1.6
0.8
1.5
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