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參數(shù)資料
| 型號： | XC4005-36XL |
| 廠商： | Xilinx, Inc. |
| 英文描述： | XC4000XL Electrical Specifications |
| 中文描述： | XC4000XL電氣規(guī)格 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 76K |
| 代理商： | XC4005-36XL |
R
DS005 (v. 1.8 October 18, 1999 - Product Specification
6-83
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Global Early Clock BUFGEs 1, 2, 5, and 6 Set-up and Hold for IFF and FCL
Speed Grade
Description
Input Setup and Hold
Times
No Delay
Global Early Clock and IFF
Global Early Clock and
FCL
-3
Min
-2
Min
-1
Min
-09
Min
-08
Min
Units
Symbol
Device
T
PSEN
/T
PHEN
T
PFSEN
/T
PFHEN
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
XC4002XL
XC4005XL
XC4010XL
XC4013XL*
XC4020XL
XC4028XL
XC4036XL*
XC4044XL
XC4052XL
XC4062XL*
XC4085XL
XC4002XL
XC4005XL
XC4010XL
XC4013XL*
XC4020XL
XC4028XL
XC4036XL*
XC4044XL
XC4052XL
XC4062XL*
XC4085XL
2.8 / 1.5
1.2 / 4.1
1.2 / 4.4
1.2 / 4.7
1.2 / 4.6
1.2 / 5.3
1.2 / 6.7
1.2 / 6.5
1.2 / 6.7
1.2 / 8.4
1.2 / 8.7
8.1 / 0.9
9.0 / 0.0
11.9 / 0.0
6.4 / 0.0
10.8 / 0.0
14.0 / 0.0
7.0 / 0.0
14.6 / 0.0
16.4 / 0.0
9.0 / 0.8
16.7 / 0.0
6.7 / 0.0
10.8 / 0.0
10.3 / 0.0
10.0 / 0.0
12.0 / 0.0
12.6 / 0.0
12.2 / 0.0
13.8 / 0.0
14.1 / 0.0
13.1 / 0.0
17.9 / 0.0
2.5 / 1.3
1.1 / 3.6
1.1 / 3.8
1.1 / 4.1
1.1 / 4.0
1.1 / 4.6
1.1 / 5.8
1.1 / 5.7
1.1 / 5.8
1.1 / 7.3
1.1 / 7.5
7.0 / 0.8
8.5 / 0.0
10.4 / 0.0
5.9 / 0.0
10.3 / 0.0
12.2 / 0.0
6.6 / 0.0
12.7 / 0.0
14.3 / 0.0
8.6 / 0.8
14.5 / 0.0
5.8 / 0.0
9.4 / 0.0
9.0 / 0.0
8.7 / 0.0
10.4 / 0.0
11.0 / 0.0
10.6 / 0.0
12.0 / 0.0
12.3 / 0.0
11.4 / 0.0
15.6 / 0.0
2.2 / 1.2
0.9 / 3.1
0.9 / 3.3
0.9 / 3.6
0.9 / 3.5
0.9 / 4.0
0.9 / 5.1
0.9 / 4.9
0.9 / 5.1
0.9 / 6.3
0.9 / 6.6
6.1 / 0.7
8.0 / 0.0
9.0 / 0.0
5.4 / 0.0
9.8 / 0.0
10.6 / 0.0
6.2 / 0.0
11.0 / 0.0
12.4 / 0.0
8.2 / 0.8
12.6 / 0.0
5.1 / 0.0
8.2 / 0.0
7.8 / 0.0
7.6 / 0.0
9.1 / 0.0
9.5 / 0.0
9.2 / 0.0
10.5 / 0.0
10.7 / 0.0
9.9 / 0.0
13.6 / 0.0
1.9 / 1.0
0.8 / 2.7
0.8 / 2.9
0.8 / 3.1
0.8 / 3.0
0.8 / 3.5
0.8 / 4.4
0.8 / 4.3
0.8 / 4.4
0.8 / 5.5
0.8 / 5.7
5.3 / 0.6
7.5 / 0.0
8.0 / 0.0
4.9 / 0.0
9.0 / 0.0
9.8 / 0.0
5.2 / 0.0
10.8 / 0.0
11.4 / 0.0
7.0 / 0.8
11.6 / 0.0
4.4 / 0.0
7.1 / 0.0
6.8 / 0.0
6.6 / 0.0
7.9 / 0.0
8.3 / 0.0
8.0 / 0.0
9.1 / 0.0
9.3 / 0.0
8.6 / 0.0
11.8 / 0.0
0.5 / 2.7
0.5 / 3.7
0.5 / 4.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Partial Delay
Global Early Clock and IFF
Global Early Clock and
FCL
T
PSEP
/T
PHEP
T
PFSEP
/T
PFHEP
4.4 / 0.0
4.7 / 0.0
6.3 / 0.5
Full Delay
Global Early Clock and IFF T
PSED
/T
PHED
6.0 / 0.0
7.2 / 0.0
7.8 / 0.0
IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch
* The XC4013XL, XC4036XL, and 4062XL have significantly faster partial and full delay setup times than other devices.
Notes:
Input setup time is measured with the fastest route and the lightest load.
Input hold time is measured using the furthest distance and a reference load of one clock pin per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin no-delay input hold specification.
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