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參數(shù)資料
| 型號： | XC4005-36XL |
| 廠商： | Xilinx, Inc. |
| 英文描述： | XC4000XL Electrical Specifications |
| 中文描述： | XC4000XL電氣規(guī)格 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 76K |
| 代理商： | XC4005-36XL |
R
DS005 (v. 1.8 October 18, 1999 - Product Specification
6-79
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XC4000XL devices and are expressed in nanoseconds unless otherwise noted.
CLB RAM Synchronous (Edge-Triggered) Write Timing Waveforms
Dual Port RAM
Speed Grade
-3
-2
--1
-09
-08
Size
Symbol
Min
Max
Min
Max
Min
Max Min Max
Min
Max
Addresswritecycletime(clockKperiod)
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
WE setup time before clock K
WE hold time after clock K
Data valid after clock K
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
T
WCDS
T
WPDS
T
ASDS
T
AHDS
T
DSDS
T
DHDS
T
WSDS
T
WHDS
T
WODS
9.0
4.5
2.5
0
2.5
0
1.8
0
7.8
8.4
4.2
2.0
0
2.3
0
1.7
0
7.3
7.7
3.9
1.7
0
2.0
0
1.6
0
6.7
7.4
3.7
1.7
0
2.0
0
1.6
0
6.7
7.4
3.7
1.6
0
2.0
0
1.6
0
6.6
X6461
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT
OLD
NEW
T
DSS
T
DHS
T
ASS
T
AHS
T
WSS
T
WPS
T
WHS
T
WOS
T
ILO
T
ILO
WCLK (K)
WE
ADDRESS
DATA IN
T
DSDS
T
DHDS
T
ASDS
T
AHDS
T
WSDS
T
WPDS
T
WHDS
X6474
DATA OUT
OLD
NEW
T
WODS
T
ILO
T
ILO
Single-Port RAM
Dual-Port RAM
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