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| 型號(hào)： | XC4005-36XL |
| 廠商： | Xilinx, Inc. |
| 英文描述： | XC4000XL Electrical Specifications |
| 中文描述： | XC4000XL電氣規(guī)格 |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大?。?/td> | 76K |
| 代理商： | XC4005-36XL |
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R
DS005 (v. 1.8 October 18, 1999 - Product Specification
6-77
XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000XL CLB Characteristics
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XC4000XL devices and are expressed in nanoseconds unless otherwise noted.
CLB Switching Characteristic Guidelines
6
Speed Grade
-3
-2
-1
-09
-08
Description
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Combinatorial Delays
F/G inputs to X/Y outputs
F/G inputs via H’ to X/Y outputs
F/G inputs via transparent latch to Q outputs
C inputs via SR/H0 via H to X/Y outputs
C inputs via H1 via H to X/Y outputs
C inputs via DIN/H2 via H to X/Y outputs
C inputs via EC, DIN/H2 to YQ, XQ output (bypass)
CLB Fast Carry Logic
Operand inputs (F1, F2, G1, G4) to C
OUT
Add/Subtract input (F3) to C
OUT
Initialization inputs (F1, F3) to C
C
IN
through function generators to X/Y outputs
C
IN
to C
OUT
, bypass function generators
Carry Net Delay, C
OUT
to C
IN
Sequential Delays
Clock K to Flip-Flop outputs Q
Clock K to Latch outputs Q
Setup Time before Clock K
F/G inputs
F/G inputs via H
C inputs via H0 through H
C inputs via H1 through H
C inputs via H2 through H
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
CIN input via F/G
CIN input via F/G and H
Hold Time after Clock K
F/G inputs
F/G inputs via H
C inputs via SR/H0 through H
C inputs via H1 through H
C inputs via DIN/H2 through H
C inputs via DIN/H2
C inputs via EC
C inputs via SR, going Low (inactive)
Clock
Clock High time
Clock Low time
Set/Reset Direct
Width (High)
Delay from C inputs via S/R, going High to Q
Global Set/Reset
Minimum GSR Pulse Width
Delay from GSR input to any Q
Toggle Frequency (MHz)
(for export control)
T
ILO
T
IHO
T
ITO
T
HH0O
T
HH1O
T
HH2O
T
CBYP
1.6
2.7
2.9
2.5
2.4
2.5
1.5
1.5
2.4
2.6
2.2
2.1
2.2
1.3
1.3
2.2
2.2
2.0
1.9
2.0
1.1
1.2
2.0
2.0
1.8
1.6
1.8
1.0
1.1
1.9
1.8
1.8
1.5
1.8
0.9
T
OPCY
T
ASCY
T
INCY
T
SUM
T
BYP
T
NET
2.7
3.3
2.0
2.8
0.26
0.32
2.3
2.9
1.8
2.6
0.23
0.28
2.0
2.5
1.5
2.4
0.20
0.25
1.6
1.8
1.0
1.7
0.14
0.24
1.6
1.8
0.9
1.5
0.14
0.24
T
CKO
T
CKLO
2.1
2.1
1.9
1.9
1.6
1.6
1.5
1.5
1.4
1.4
T
ICK
T
IHCK
T
HH0CK
T
HH1CK
T
HH2CK
T
DICK
T
ECCK
T
RCK
T
CCK
T
CHCK
1.1
2.2
2.0
1.9
2.0
0.9
1.0
0.6
2.3
3.4
1.0
1.9
1.7
1.6
1.7
0.8
0.9
0.5
2.1
3.0
0.9
1.7
1.6
1.4
1.6
0.7
0.8
0.5
1.9
2.7
0.8
1.6
1.4
1.2
1.4
0.6
0.7
0.4
1.3
2.1
0.8
1.5
1.4
1.1
1.4
0.6
0.7
0.4
1.2
2.0
T
CKI
T
CKIH
T
CKHH0
T
CKHH1
T
CKHH2
T
CKDI
T
CKEC
T
CKR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
T
CH
T
CL
3.0
3.0
2.8
2.8
2.5
2.5
2.3
2.3
2.1
2.1
T
RPW
T
RIO
3.0
3.7
2.8
3.2
2.5
2.8
2.3
2.7
2.3
2.6
T
MRW
T
MRQ
F
TOG
(MHz)
19.8
17.3
15.0
14.0
14.0
See
Table on page 85
for T
RRI
values per device.
166
179
200
217
238
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