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參數(shù)資料
| 型號： | XC3SD1800A-4CSG484LI |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 61/101頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN 3 DSP 484CSGBGA |
| 標準包裝： | 84 |
| 系列： | Spartan®-3A DSP |
| LAB/CLB數(shù)： | 4160 |
| 邏輯元件/單元數(shù)： | 37440 |
| RAM 位總計： | 1548288 |
| 輸入/輸出數(shù)： | 309 |
| 門數(shù)： | 1800000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 484-FBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 484-CSPBGA |
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DS610 (v3.0) October 4, 2010
Product Specification
62
Copyright 2007–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
Introduction
This section describes how the various pins on a Spartan-3A DSP FPGA connect within the supported component
packages and provides device-specific thermal characteristics. For general information on the pin functions and the package
characteristics, see the Packaging section in UG331: Spartan-3 Generation FPGA User Guide.
Spartan-3A DSP FPGAs are available in both standard and Pb-free, RoHS versions of each package, with the Pb-free
version adding a “G” to the middle of the package code. Except for the thermal characteristics, all information for the
standard package applies equally to the Pb-free package.
Pin Types
Most pins on a Spartan-3A DSP FPGA are general-purpose, user-defined I/O pins. There are, however, up to 12 different
functional types of pins on Spartan-3A DSP packages, as outlined in Table 57. In the package footprint drawings that follow,
the individual pins are color-coded according to pin type as in the table.
101
Spartan-3A DSP FPGA Family:
Pinout Descriptions
DS610 (v3.0) October 4, 2010
Product Specification
Table 57: Types of Pins on Spartan-3A DSP FPGAs
Type/Color
Code
Description
Pin Name(s) in Type
I/O
Unrestricted, general-purpose user-I/O pin. Most pins can be paired together to form
differential I/Os.
IO_#
IO_Lxxy_#
INPUT
Unrestricted, general-purpose input-only pin. This pin does not have an output structure,
differential termination resistor, or PCI clamp diode.
IP_#
IP_Lxxy_#
DUAL
Dual-purpose pin used in some configuration modes during the configuration process and
then usually available as a user I/O after configuration. If the pin is not used during
configuration, this pin behaves as an I/O-type pin. See UG332: Spartan-3 Generation
Configuration User Guide for additional information on these signals.
M[2:0]
PUDC_B
CCLK
MOSI/CSI_B
D[7:1]
D0/DIN
CSO_B
RDWR_B
INIT_B
A[25:0]
VS[2:0]
LDC[2:0]
HDC
VREF
Dual-purpose pin that is either a user-I/O pin or Input-only pin, or, along with all other VREF
pins in the same bank, provides a reference voltage input for certain I/O standards. If used for
a reference voltage within a bank, all VREF pins within the bank must be connected.
IP/VREF_#
IP_Lxxy_#/VREF_#
IO/VREF_#
IO_Lxxy_#/VREF_#
CLK
Either a user-I/O pin or an input to a specific clock buffer driver. Packages have 16 global clock
inputs that optionally clock the entire device. The RHCLK inputs optionally clock the right half
of the device. The LHCLK inputs optionally clock the left half of the device. See the Using
Global Clock Resources chapter in UG331: Spartan-3 Generation FPGA User Guide for
additional information on these signals.
IO_Lxxy_#/GCLK[15:0],
IO_Lxxy_#/LHCLK[7:0],
IO_Lxxy_#/RHCLK[7:0]
CONFIG
Dedicated configuration pin, two per device. Not available as a user-I/O pin. Every package
has two dedicated configuration pins. These pins are powered by VCCAUX. See the UG332:
Spartan-3 Generation Configuration User Guide for additional information on the DONE and
PROG_B signals.
DONE, PROG_B
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