參數(shù)資料
型號： XC3SD1800A-4CSG484LI
廠商： Xilinx Inc
文件頁數(shù)： 60/101頁
文件大?。?/td> 0K
描述： IC FPGA SPARTAN 3 DSP 484CSGBGA
標準包裝： 84
系列： Spartan®-3A DSP
LAB/CLB數(shù)： 4160
邏輯元件/單元數(shù)： 37440
RAM 位總計： 1548288
輸入/輸出數(shù)： 309
門數(shù)： 1800000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 484-FBGA，CSPBGA
供應商設備封裝： 484-CSPBGA
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
DS610 (v3.0) October 4, 2010
Product Specification
61
Revision History
The following table shows the revision history for this document.
Date
Version
Revision
04/02/07
1.0
Initial Xilinx release.
05/25/07
1.0.1
Minor edits.
06/18/07
1.2
Updated for v1.29 production speed files. Noted banking rules in Table 11 and Table 12. Added
DIFF_HSTL_I and DIFF_HSTL_III to Table 12, Table 13, and Table 26. Updated TMDS DC characteristics
in Table 13. Updated I/O Test Method values in Table 26. Added Simultaneously Switching Output limits in
Table 28. Updated DSP48A timing symbols, descriptions, and values in Table 34. Added power-on timing in
Table 45. Added CCLK specifications for Commercial in Table 46 through Table 48. Updated Slave Parallel
timing in Table 51. Updated JTAG specifications in Table 56.
07/16/07
2.0
Added Low-power options and updated typical values for quiescent current in Table 9. Updated DSP48A
timing in Table 34 and Table 35.
06/02/08
2.1
Improved VCCAUXT and VCCO2T POR minimum in Table 4 and updated VCCO POR levels in Figure 10. Added
VIN to Recommended Operating Conditions in Table 7 and added reference to XAPP459, “Eliminating I/O
Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins.” Reduced typical
ICCINTQ and ICCAUXQ quiescent current values by 20%-44% in Table 9. Increased VIL max to 0.4V for
LVCMOS12/15/18 and improved VIH min to 0.7V for LVCMOS12 in Table 10. Changed VOL max to 0.4V and
VOH min to VCCO–0.4V for LVCMOS15/18 in Table 11. Added reference to VCCAUX in Simultaneously
Switching Output Guidelines. Removed DNA_RETENTION limit of 10 years in Table 14 since number of
Read cycles is the only unique limit. Updated speed files to v1.31 in Table 16 and elsewhere. Updated IOB
Setup and Hold times with device-specific values in Table 19. Added reference to Sample Window in
Table 20. Updated IOB Propagation times with device-specific values in Table 21. Improved SSTL_18_II
SSO value in Table 28. Improved FBUFG for -4 to 334 MHz in Table 32. Added references to 375 MHz
performance via SCD 4103 in Table 32,Table 37, Table 38, and Table 39. Added explanatory footnotes to
DSP48A Timing tables. Simplified DSP48A FMAX to value with all registers used in Table 35. Improved
FBUFG in Table 32 for -4 speed grade. Updated CCLK output maximum period in Table 46 to match
minimum frequency in Table 47. Replaced BPI with SPI specification descriptions in Table 52. Corrected BPI
Figure 14 and Table 54 from falling edge to rising edge. Added references to Spartan-3 Generation User
Guides. Updated links.
03/11/09
2.2
Changed typical quiescent current temperature from ambient to quiescent. Updated selected I/O standard
DC characteristics. Removed PCIX IOSTANDARD due to limited PCIX interface support. Added TIOPI and
TIOPID to Table 21. Updated BPI configuration waveforms in Figure 14 and updated Table 55. Removed
references to SCD 4103.
10/04/10
3.0
Added IIK to Table 3. Updated description for VIN in Table 7 including adding note 4. Also, added note 2 to IL
in Table 8 to note potential leakage between pins of a differential pair. Added note 6 to Table 10. Updated
notes 5 and 6 in Table 12. Corrected symbols for TSUSPEND_GTS and TSUSPEND_GWE in Table 44.
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