參數(shù)資料
型號(hào): XC3SD1800A-4CSG484LI
廠商: Xilinx Inc
文件頁(yè)數(shù): 15/101頁(yè)
文件大?。?/td> 0K
描述: IC FPGA SPARTAN 3 DSP 484CSGBGA
標(biāo)準(zhǔn)包裝: 84
系列: Spartan®-3A DSP
LAB/CLB數(shù): 4160
邏輯元件/單元數(shù): 37440
RAM 位總計(jì): 1548288
輸入/輸出數(shù): 309
門數(shù): 1800000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 484-FBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 484-CSPBGA
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
DS610 (v3.0) October 4, 2010
Product Specification
20
I/O Timing
Pin-to-Pin Clock-to-Output Times
Table 17: Pin-to-Pin Clock-to-Output Times for the IOB Output Path
Symbol
Description
Conditions
Device
Speed Grade
Units
-5
-4
Max
Clock-to-Output Times
TICKOFDCM
When reading from the Output
Flip-Flop (OFF), the time from the
active transition on the Global
Clock pin to data appearing at the
Output pin. The DCM is in use.
LVCMOS25(2), 12 mA
output drive, Fast slew
rate, with DCM(3)
XC3SD1800A
3.28
3.51
ns
XC3SD3400A
3.36
3.82
ns
TICKOF
When reading from OFF, the time
from the active transition on the
Global Clock pin to data appearing
at the Output pin. The DCM is not
in use.
LVCMOS25(2), 12 mA
output drive, Fast slew
rate, without DCM
XC3SD1800A
5.23
5.58
ns
XC3SD3400A
5.51
6.13
ns
Notes:
1.
The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
2.
This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a
standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate
Input adjustment from Table 22. If the latter is true, add the appropriate Output adjustment from Table 25.
3.
DCM output jitter is included in all measurements.
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