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參數(shù)資料
| 型號： | XC3SD1800A-4CSG484LI |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 36/101頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN 3 DSP 484CSGBGA |
| 標準包裝： | 84 |
| 系列： | Spartan®-3A DSP |
| LAB/CLB數(shù)： | 4160 |
| 邏輯元件/單元數(shù)： | 37440 |
| RAM 位總計： | 1548288 |
| 輸入/輸出數(shù)： | 309 |
| 門數(shù)： | 1800000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 484-FBGA，CSPBGA |
| 供應商設備封裝： | 484-CSPBGA |
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Spartan-3A DSP FPGA Family: Introduction and Ordering Information
DS610 (v3.0) October 4, 2010
Product Specification
4
Configuration
Spartan-3A DSP FPGAs are programmed by loading
configuration data into robust, reprogrammable, static
CMOS configuration latches (CCLs) that collectively control
all functional elements and routing resources. The FPGA’s
configuration data is stored externally in a PROM or some
other non-volatile medium, either on or off the board. After
applying power, the configuration data is written to the
FPGA using any of seven different modes:
Master Serial from a Xilinx Platform Flash PROM
Serial Peripheral Interface (SPI) from an
industry-standard SPI serial Flash
Byte Peripheral Interface (BPI) Up from an
industry-standard x8 or x8/x16 parallel NOR Flash
Slave Serial, typically downloaded from a processor
Slave Parallel, typically downloaded from a processor
Boundary Scan (JTAG), typically downloaded from a
processor or system tester
Furthermore, Spartan-3A DSP FPGAs support MultiBoot
configuration, allowing two or more FPGA configuration
bitstreams to be stored in a single SPI serial Flash or a BPI
parallel NOR Flash. The FPGA application controls which
configuration to load next and when to load it.
Additionally, each Spartan-3A DSP FPGA contains a
unique, factory-programmed Device DNA identifier useful
for tracking purposes, anti-cloning designs, or IP protection.
I/O Capabilities
The Spartan-3A DSP FPGA SelectIO interface supports
many popular single-ended and differential standards.
Table 2 shows the number of user I/Os as well as the
number of differential I/O pairs available for each
device/package combination. Some of the user I/Os are
unidirectional input-only pins as indicated in Table 2.
Spartan-3A DSP FPGAs support the following single-ended
standards:
3.3V low-voltage TTL (LVTTL)
Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
1.5V, or 1.2V
3.3V PCI at 33 MHz or 66 MHz
HSTL I, II, and III at 1.5V and 1.8V, commonly used in
memory applications
SSTL I and II at 1.8V, 2.5V, and 3.3V, commonly used
for memory applications
Spartan-3A DSP FPGAs support the following
differential standards:
LVDS, mini-LVDS, RSDS, and PPDS I/O at 2.5V or
3.3V
Bus LVDS I/O at 2.5V
TMDS I/O at 3.3V
Differential HSTL and SSTL I/O
LVPECL inputs at 2.5V or 3.3V
Table 2: Available User I/Os and Differential (Diff) I/O Pairs
Device
CS484
CSG484
FG676
FGG676
User
Diff
User
Diff
XC3SD1800A
309(1)
(60)
140
(78)
519
(110)
227
(131)
XC3SD3400A
309
(60)
140
(78)
469
(60)
213
(117)
Notes:
1.
The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number of
input-only pins. The differential (Diff) input-only pin count includes both differential pairs on input-only pins and differential pairs on I/O pins within I/O
banks that are restricted to differential inputs.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XC3SD1800A-4FG676C | 制造商:Xilinx 功能描述:FPGA SPARTAN-3A 1.8M GATES 37440 CELLS 667MHZ 1.2V 676FBGA - Trays 制造商:Xilinx 功能描述:IC FPGA 519 I/O 676FBGA 制造商:Xilinx 功能描述:SPARTAN-3ADSP FPGA 1800K 676FBGA |
| XC3SD1800A-4FG676I | 功能描述:SPARTAN-3ADSP FPGA 1800K 676FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3A DSP 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應商設備封裝:676-FBGA（27x27） |
| XC3SD1800A-4FGG676C | 功能描述:SPARTAN-3ADSP FPGA 1800K 676FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3A DSP 標準包裝:24 系列:ECP2 LAB/CLB數(shù):1500 邏輯元件/單元數(shù):12000 RAM 位總計:226304 輸入/輸出數(shù):131 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:208-BFQFP 供應商設備封裝:208-PQFP（28x28） |
| XC3SD1800A-4FGG676CES | 制造商:Xilinx 功能描述: |
| XC3SD1800A-4FGG676I | 功能描述:SPARTAN-3ADSP FPGA 1800K 676FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3A DSP 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應商設備封裝:676-FBGA（27x27） |
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