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參數(shù)資料
| 型號(hào)： | XC3S1000-4VQ100C |
| 廠(chǎng)商： | XILINX INC |
| 元件分類(lèi)： | FPGA |
| 英文描述： | Spartan-3 FPGA Family: Complete Data Sheet |
| 中文描述： | FPGA, 192 CLBS, 50000 GATES, PQFP100 |
| 封裝： | VQFP-100 |
| 文件頁(yè)數(shù)： | 91/198頁(yè) |
| 文件大?。?/td> | 1605K |
| 代理商： | XC3S1000-4VQ100C |
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Spartan-3 FPGA Family: Pinout Descriptions
DS099-4 (v1.6) January 17, 2005
Product Specification
www.xilinx.com
5
R
DONE
Bidirectional with open-drain
or totem-pole Output
Configuration Done, Delay Start-up Sequence:
A Low-to-High output transition on this bidirectional pin signals the
end of the configuration process.
The FPGA produces a Low-to-High transition on this pin to
indicate that the configuration process is complete. The DriveDone
bitstream generation option defines whether this pin functions as
a totem-pole output that actively drives High or as an open-drain
output. An open-drain output requires a pull-up resistor to produce
a High logic level. The open-drain option permits the DONE lines
of multiple FPGAs to be tied together, so that the common node
transitions High only after all of the FPGAs have completed
configuration. Externally holding the open-drain output Low delays
the start-up sequence, which marks the transition to user mode.
M0, M1, M2
Input
Configuration Mode Selection:
These inputs select the configuration mode. The logic levels
applied to the mode pins are sampled on the rising edge of INIT_B.
See
Table 7
.
HSWAP_EN
Input
Disable Weak Pull-up Resistors During Configuration:
A Low on this pin enables weak pull-up resistors on all pins that are
not actively involved in the configuration process. A High value
disables all pull-ups, allowing the non-configuration pins to float.
JTAG:
JTAG interface pins
TCK
Input
JTAG Test Clock:
The TCK clock signal synchronizes all JTAG port operations.
TDI
Input
JTAG Test Data Input:
TDI is the serial data input for all JTAG instruction and data
registers.
TMS
Input
JTAG Test Mode Select:
The serial TMS input controls the operation of the JTAG port.
TDO
Output
JTAG Test Data Output:
TDO is the serial data output for all JTAG instruction and data
registers.
VCCO:
I/O bank output voltage supply pins
VCCO_#
Supply
Power Supply for Output Buffer Drivers (per bank):
These pins power the output drivers within a specific I/O bank.
VCCAUX:
Auxiliary voltage supply pins
VCCAUX
Supply
Power Supply for Auxiliary Circuits:
+2.5V power pins for auxiliary circuits, including the Digital Clock
Managers (DCMs), the dedicated configuration pins (CONFIG),
and the dedicated JTAG pins. All VCCAUX pins must be
connected.
VCCINT:
Internal core voltage supply pins
VCCINT
Supply
Power Supply for Internal Core Logic:
+1.2V power pins for the internal logic. All pins must be connected.
Table 2:
Spartan-3 Pin Definitions
(Continued)
Pin Name
Direction
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC3S1000-4VQ100I | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4VQG100C | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4VQG100I | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-5CP132C | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-5CP132I | Spartan-3 FPGA Family: Complete Data Sheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3S1000-4VQ100I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA |
| XC3S1000-4VQG100C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4VQG100I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-5CP132C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA |
| XC3S1000-5CP132I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA |
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