
Spartan-3 FPGA Family: DC and Switching Characteristics
2
www.xilinx.com
DS099-3 (v1.5) December 17, 2004
Advance Product Specification
R
T
J
Junction temperature
V
CCO
< 3.0V
-
125
°C
V
CCO
> 3.0V
-
105
°C
T
STG
Storage temperature
–65
150
°C
Notes:
1.
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time adversely
affects device reliability.
As a rule, the V
IN
limits apply to both the DC and AC components of signals. Simple application solutions are available that show
how to handle overshoot/undershoot as well as achieve PCI compliance. Refer to the following application notes: "Virtex-II Pro
and Spartan-3 3.3V PCI Reference Design" (
XAPP653
) and "Using 3.3V I/O Guidelines in a Virtex-II Pro Design" (
XAPP659
).
All User I/O and Dual-Purpose pins (DIN/D0, D1–D7, CS_B, RDWR_B, BUSY/DOUT, and INIT_B) draw power from the V
CCO
power rail of the associated bank. Meeting the V
IN
max limit ensures that the internal diode junctions that exist between each of
these pins and the V
CCO
rail do not turn on.
Table 5
specifies the V
CCO
range used to determine the max limit. When V
CCO
is at its
maximum recommended operating level (3.45V), V
IN
max is 3.95V. The maximum voltage that avoids oxide stress is V
INX
= 4.05V.
As long as the V
IN
max specification is met, oxide stress is not possible.
All Dedicated pins (M0–M2, CCLK, PROG_B, DONE, HSWAP_EN, TCK, TDI, TDO, and TMS) draw power from the V
CCAUX
rail
(2.5V). Meeting the V
IN
max limit ensures that the internal diode junctions that exist between each of these pins and the V
CCAUX
rail
do not turn on.
Table 5
specifies the V
CCAUX
range used to determine the max limit. When V
CCAUX
is at its maximum recommended
operating level (2.625V), V
IN
max < 3.125V. As long as the V
IN
max specification is met, oxide stress is not possible. For information
concerning the use of 3.3V signals, see the
3.3V-Tolerant Configuration Interface
section in Module 2:
Functional Description
.
For soldering guidelines, see "Device Packaging and Thermal Characteristics" at
www.xilinx.com/bvdocs/userguides/ug112.pdf
.
2.
3.
4.
5.
Table 1:
Absolute Maximum Ratings
(Continued)
Symbol
Description
Conditions
Min
Max
Units
Table 2:
Supply Voltage Thresholds for Power-On Reset
Symbol
Description
Min
Max
Units
V
CCINTT
V
CCAUXT
V
CCO4T
Threshold for the V
CCINT
supply
Threshold for the V
CCAUX
supply
Threshold for the V
CCO
Bank 4 supply
0.4
1.0
V
0.8
2.0
V
0.4
1.0
V
Notes:
1.
V
CCINT
, V
CCAUX
, and V
CCO
supplies may be applied in any order. When applying V
CCINT
power before V
CCAUX
power, the FPGA may
draw a
surplus
current in addition to the quiescent current levels specified in
Table 7
. Applying V
CCAUX
eliminates the surplus current.
The FPGA does not use any of the surplus current for the power-on process. For this power sequence, make sure that regulators
with foldback features will not shut down inadvertently.
To ensure successful power-on, V
CCINT
, V
CCO
Bank 4, and V
CCAUX
supplies must rise through their respective threshold-voltage
ranges with no dips at any point.
2.