- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374986 > XC3S1000-4VQ100C (XILINX INC) Spartan-3 FPGA Family: Complete Data Sheet PDF資料下載
參數(shù)資料
| 型號(hào)： | XC3S1000-4VQ100C |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Spartan-3 FPGA Family: Complete Data Sheet |
| 中文描述： | FPGA, 192 CLBS, 50000 GATES, PQFP100 |
| 封裝： | VQFP-100 |
| 文件頁(yè)數(shù)： | 76/198頁(yè) |
| 文件大小： | 1605K |
| 代理商： | XC3S1000-4VQ100C |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)當(dāng)前第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)
Spartan-3 FPGA Family: DC and Switching Characteristics
DS099-3 (v1.5) December 17, 2004
Advance Product Specification
39
www.xilinx.com
29
R
Digital Clock Manager (DCM) Timing
For specification purposes, the DCM consists of three key
components: the Delay-Locked Loop (DLL), the Digital Fre-
quency Synthesizer (DFS), and the Phase Shifter (PS).
Aspects of DLL operation play a role in all DCM applica-
tions. All such applications inevitably use the CLKIN and the
CLKFB inputs connected to either the CLK0 or the CLK2X
feedback, respectively. Thus, specifications in the DLL
tables (
Table 28
and
Table 29
) apply to any application that
only employs the DLL component. When the DFS and/or
the PS components are used together with the DLL, then
the specifications listed in the DFS and PS tables (
Table 30
through
Table 33
) supersede any corresponding ones in the
DLL tables. DLL specifications that do not change with the
addition of DFS or PS functions are presented in
Table 28
and
Table 29
.
Period jitter and cycle-cycle jitter are two (of many) different
ways of characterizing clock jitter. Both specifications
describe statistical variation from a mean value.
Period jitter is the worst-case deviation from the average
clock period of all clock cycles in the collection of clock peri-
ods sampled (usually from 100,000 to more than a million
samples for specification purposes). In a histogram of
period jitter, the mean value is the clock period.
Cycle-cycle jitter is the worst-case difference in clock period
between adjacent clock cycles in the collection of clock peri-
ods sampled. In a histogram of cycle-cycle jitter, the mean
value is zero.
Table 28:
Recommended Operating Conditions for the DLL
Symbol
Description
Device
Revision
Frequency
Mode/
F
CLKIN
Range
Speed Grade
Units
-5
-4
Min
Max
Min
Max
Input Frequency Ranges
F
CLKIN
CLKIN_FREQ_DLL_LF
Frequency for the
CLKIN input
All
Low
24
(2)
167
(3)
24
(2)
165
(3)
MHz
CLKIN_FREQ_DLL_HF
High
48
280
(3)
48
280
(3)
MHz
Input Pulse Requirements
CLKIN_PULSE
CLKIN pulse width as
a percentage of the
CLKIN period
0
F
CLKIN
< 100 MHz
F
CLKIN
> 100 MHz
40%
60%
40%
60%
-
45%
55%
45%
55%
-
Input Clock Jitter and Delay Path Variation
CLKIN_CYC_JITT_DLL_LF
Cycle-to-cycle jitter at
the CLKIN input
All
Low
-261
+261
-300
+300
ps
CLKIN_CYC_JITT_DLL_HF
High
-131
+131
-150
+150
ps
CLKIN_PER_JITT_DLL_LF
Period jitter at the
CLKIN input
All
-0.87
+0.87
-1
+1
ns
CLKIN_PER_JITT_DLL_HF
CLKFB_DELAY_VAR_EXT
Allowable variation of
off-chip feedback delay
from the DCM output
to the CLKFB input
All
-0.87
+0.87
-1
+1
ns
Notes:
1.
2.
3.
DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
Use of the DFS permits lower F
CLKIN
frequencies. See
Table 30
.
To double the maximum effective F
CLKIN
limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC3S1000-4VQ100I | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4VQG100C | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4VQG100I | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-5CP132C | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-5CP132I | Spartan-3 FPGA Family: Complete Data Sheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3S1000-4VQ100I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA |
| XC3S1000-4VQG100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-4VQG100I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-5CP132C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA |
| XC3S1000-5CP132I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。