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參數(shù)資料
| 型號： | W9751G6JB-25A |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 0.4 ns, PBGA84 |
| 封裝： | 12.50 X 8 MM, ROHS COMPLIANT, WBGA-84 |
| 文件頁數(shù)： | 4/86頁 |
| 文件大?。?/td> | 1030K |
| 代理商： | W9751G6JB-25A |
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W9751G6JB
Publication Release Date: Mar. 10, 2010
- 12 -
Revision A02
7.2.2.2
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization,
and upon returning to normal operation after having the DLL disabled. The DLL is automatically
disabled when entering Self Refresh operation and is automatically re-enabled and reset upon exit of
Self Refresh operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must
occur before a Read command can be issued to allow time for the internal clock to be synchronized
with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC
or tDQSCK parameters.
BA1
BA0 A12
A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
1
OCD program
BT
Rtt
Address Field
Extended Mode Register (1)
BA1 BA0
MRS mode
0
1
11
MR
EMR (1)
EMR (2)
EMR (3)
A6
A2
0
1
11
WR
Additive Latency
Qoff
0*
1
DQS
Rtt D.I.C DLL
Rtt (nominal)
ODT Disabled
75 ohm
150 ohm
50 ohm*2
0
A0
1
DLL Enable
Enable
Disable
OCD Calibration Program
OCD calibration mode exit; matain setting
Adjust mode*3
OCD Calibration default*4
Drive (1)
Drive (0)
A9
A8
A7
1
00
0
11
1
00
0
Driver impedance adjustment
A12
1
0
Output buffer enabled
Qoff (Optional)*5
Output buffer disabled
A10
1
0
DQS
Enable
Disable
A10
(DQS Enable)
0 (Enable)
1 (Disable)
Strobe Function Matrix
DQS
Hi-z
Output driver
impedance control
Reduced
Normal
A1
0
1
A5
0
1
A4
0
1
0
1
A3
0
1
0
1
0
1
0
Latency
0
3
4
Reserved
1
2
Output Driver Impedance Control
Driver
size
100%
60%
Additive Latency
5
6
DDR2
-/
66
7/
800
DD
R2-
1066
Notes:
1. A11 default is “0 “ RDQS disabled.
2. Optional for DDR2-667, mandatory for DDR2-800 and DDR2-1066.
3. When Adjust mode is issued, AL from previously set value must be applied.
4. After setting to default, OCD calibration mode needs to be exited by setting A9-A7 to 000. Refer to the section 7.2.3 for
detailed information.
5. Output disabled - DQs, LDQS, LDQS , UDQS, UDQS . This feature is used in conjunction with DIMM IDD measurements
when IDDQ is not desired to be included.
Figure 3—EMR (1)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W9751G6JB-3 | 制造商:Winbond Electronics Corp 功能描述:512MB DDRII |
| W9751G6KB | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M ? 4 BANKS ? 16 BIT DDR2 SDRAM |
| W9751G6KB-18 | 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W9751G6KB-25 | 功能描述:IC DDR2 SDRAM 512MBIT 84WBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:4G（256M x 16） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP I 包裝:Digi-Reel® 其它名稱:557-1461-6 |
| W9751G6KB25A | 制造商:WINBOND 制造商全稱:Winbond 功能描述:Double Data Rate architecture: two data transfers per clock cycle |
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