參數(shù)資料
型號: W9751G6JB-25A
廠商: WINBOND ELECTRONICS CORP
元件分類: DRAM
英文描述: 32M X 16 DDR DRAM, 0.4 ns, PBGA84
封裝: 12.50 X 8 MM, ROHS COMPLIANT, WBGA-84
文件頁數(shù): 35/86頁
文件大小: 1030K
代理商: W9751G6JB-25A
W9751G6JB
Publication Release Date: Mar. 10, 2010
- 40 -
Revision A02
9.9
DC Characteristics
(0≤ TCASE ≤ 85for -18/-25/-3, -40≤ TCASE ≤ 95for 25I/25A, VDD, VDDQ = 1.8V ± 0.1V)
-18
-25
25I
25A
-3
SYM.
CONDITIONS
MAX.
UNIT
NOTES
IDD0
Operating Current - One Bank Active-Precharge
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD);
CKE is HIGH, CS is HIGH between valid commands;
Address and control inputs are SWITCHING;
Databus inputs are SWITCHING.
75
70
65
mA
1,2,3,4,5,
6
IDD1
Operating Current - One Bank Active-Read-
Precharge
IOUT = 0 mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD), tRCD
= tRCD(IDD);
CKE is HIGH, CS is HIGH between valid commands;
Address and control inputs are SWITCHING;
Data bus inputs are SWITCHING.
85
80
75
mA
1,2,3,4,5,
6
IDD2P
Precharge Power-Down Current
All banks idle;
tCK = tCK(IDD);
CKE is LOW;
Other control and address inputs are STABLE;
Data Bus inputs are FLOATING.
8
mA
1,2,3,4,5,
6
IDD2N
Precharge Standby Current
All banks idle;
tCK = tCK(IDD);
CKE is HIGH, CS is HIGH;
Other control and address inputs are SWITCHING;
Data bus inputs are SWITCHING.
45
40
35
mA
1,2,3,4,5,
6
IDD2Q
Precharge Quiet Standby Current
All banks idle;
tCK = tCK(IDD);
CKE is HIGH, CS is HIGH;
Other control and address inputs are STABLE;
Data bus inputs are FLOATING.
35
30
mA
1,2,3,4,5,
6
IDD3PF
Fast PDN Exit
MRS(12) = 0
15
IDD3PS
Active Power-Down Current
All banks open;
tCK = tCK(IDD);
CKE is LOW;
Other control and address inputs are
STABLE;
Data bus inputs are FLOATING.
Slow PDN Exit
MRS(12) = 1
12
mA
1,2,3,4,5,
6
IDD3N
Active Standby Current
All banks open;
tCK = tCK(IDD); tRAS = tRASmax(IDD), tRP = tRP(IDD);
CKE is HIGH, CS is HIGH between valid commands;
Other control and address inputs are SWITCHING;
Data bus inputs are SWITCHING.
60
50
45
mA
1,2,3,4,5,
6
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