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參數(shù)資料
| 型號： | W9751G6JB-25A |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 0.4 ns, PBGA84 |
| 封裝： | 12.50 X 8 MM, ROHS COMPLIANT, WBGA-84 |
| 文件頁數(shù)： | 19/86頁 |
| 文件大?。?/td> | 1030K |
| 代理商： | W9751G6JB-25A |
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W9751G6JB
Publication Release Date: Mar. 10, 2010
- 26 -
Revision A02
7.4.5
Write data mask
One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAM,
consistent with the implementation on DDR1 SDRAM. It has identical timings on write operations as
the data bits, and though used in a unidirectional manner, is internally loaded identically to data bits to
insure matched system timing. DM is not used during read cycles. (Example timing waveform refer to
10.15 Write operation with Data Mask diagram in Chapter 10)
7.5 Burst Interrupt
Read or Write burst interruption is prohibited for burst length of 4 and only allowed for burst length of 8
under the following conditions:
1. Read burst of 8 can only be interrupted by another Read command. Read burst interruption by
Write or Precharge Command is prohibited.
2. Write burst of 8 can only be interrupted by another Write command. Write burst interruption by
Read or Precharge Command is prohibited.
3. Read burst interrupt must occur exactly two clocks after the previous Read command. Any other
Read burst interrupt timings are prohibited.
4. Write burst interrupt must occur exactly two clocks after the previous Write command. Any other
Write burst interrupt timings are prohibited.
5. Read or Write burst interruption is allowed to any bank inside the DDR2 SDRAM.
6. Read or Write burst with Auto-precharge enabled is not allowed to interrupt.
7. Read burst interruption is allowed by a Read with Auto-precharge command.
8. Write burst interruption is allowed by a Write with Auto-precharge command.
9. All command timings are referenced to burst length set in the mode register. They are not
referenced to the actual burst. For example below:
Minimum Read to Precharge timing is AL + BL/2 where BL is the burst length set in the
mode register and not the actual burst (which is shorter because of interrupt).
Minimum Write to Precharge timing is WL + BL/ 2 + tWR, where tWR starts with the rising
clock after the un-interrupted burst end and not from the end of the actual burst end.
(Example timing waveforms refer to 10.13 and 10.14 Burst read and write interrupt timing diagram in
Chapter 10)
相關PDF資料 |
PDF描述 |
|---|---|
| W9751G8JB-18 | DDR DRAM, PBGA84 |
| W9812G21H-6I | 4M X 32 SYNCHRONOUS DRAM, 5 ns, PDSO86 |
| W9812G21H-6C | 4M X 32 SYNCHRONOUS DRAM, 4.5 ns, PDSO86 |
| W9812G6JH-6 | 8M X 16 SYNCHRONOUS DRAM, 5 ns, PDSO54 |
| W986416AH-10 | 4M X 16 SYNCHRONOUS DRAM, 8 ns, PDSO54 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| W9751G6JB-3 | 制造商:Winbond Electronics Corp 功能描述:512MB DDRII |
| W9751G6KB | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M ? 4 BANKS ? 16 BIT DDR2 SDRAM |
| W9751G6KB-18 | 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W9751G6KB-25 | 功能描述:IC DDR2 SDRAM 512MBIT 84WBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:4G（256M x 16） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應商設備封裝:48-TSOP I 包裝:Digi-Reel® 其它名稱:557-1461-6 |
| W9751G6KB25A | 制造商:WINBOND 制造商全稱:Winbond 功能描述:Double Data Rate architecture: two data transfers per clock cycle |
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