
W925E/C625
8-bit CID Microcontroller
sets the bit FDR and converts the 8-bit serial data into the byte register FSKDR. The rising edge
of bit FDR will set the flag FDRF to produce CID interrupt but FDRF is cleared by software. User
can get the FSK data by reading register FSKDR or sampling the bit FDATA. The timing of FSK
demodulation is shown in Figure 6-24.
Revision : A6
-57-
Release Date : 2002/7/2
Tip/Ring
1*
1
0
b0
b1
b2
start
b3
b4
b5 b6
b7 1*
0
b0
b1 b2
b3
b4 b5
b6 b7
1
1
0
b0
stop
start
stop
start
FDATA
b0
b1 b2
b3
b4 b5
b6 b7
b0 b1
b2
b3 b4
b5 b6
b7
start
stop
start
stop
start
t
IDD
FCLK
FDR
1/f
DCLK0
t
CRD
t
RH
1st byte data
2nd byte data
1st byte data
2nd byte data
* Mark bit or redundant stop bit(s), will be omitted.
+ Clear by software.
FDRF
+
FSKDR
1st byte data
2nd byte data
Figure 6-24 Serial Data Interface Timing of FSK Demodulation
CID Input Gain Control
The CID input gain and input hysteresis are controllable by internal CID gain control registers.
CIDGD and CIDGA registers determine the 6 internal CID gain control registers. CID gain control
data register (CIDGD) presents the data bus. The lower 3 bits of CID gain control address register
(CIDGA) presents the address. The rising edge of CIDGA.4 will latch the CIDGD in the
corresponding internal CID gain control register. The 6 internal CID gain control registers are
addressed as following table. Setting the 6 registers as the suggestion value guarantees the CID
spec.
Address
(CIDGA.2-0)
000
DTMFR1
: DTMF register1
001
DTMFR2
: DTMF register2
002
PGAF
: Programmable gain control alert tone and FSK
003
PGAD
: Programmable gain control DTMF
004
PHAD
: Programmable hysteresis alert tone and DTMF
005
PHFL
: Programmable hysteresis FSK and low pass filter
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X=0 DTMF receiver works a DTMF decoder, X=1 DTMF receiver works as a tone detector.
The signals to set internal CID gain control registers is shown in Figure 6-25
Internal CID Gain Control Register
Suggestion
Value
0000 0001B
011X 0001B
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99H
A7H
35H
33H