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參數(shù)資料
| 型號： | W925E625 |
| 英文描述： | Telephone Controller |
| 中文描述： | 電話控制器 |
| 文件頁數(shù)： | 53/71頁 |
| 文件大小： | 1055K |
| 代理商： | W925E625 |
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W925E/C625
8-bit CID Microcontroller
Ring Detector
The application circuit in Figure 6-18 illustrates the relationship between the RNGDI, RNGRC and
RNG signals. The combination of RNGDI and RNGRC is used to detect an increase of the
RNGDI voltage from ground to a level above the Schmitt trigger high going threshold voltage V
T+
.
Revision : A6
-53-
Release Date : 2002/7/2
Tip/A
R1=470K
C1=0.1uF
Ring/B
C1=0.1uF
C3=0.22uF
R5=150K
R2=470K
R3=200K
R4=300K
RNGDI
RNGRC
RNG
Allowance minimal ring voltage (peak to peak) is:
Vpp
(max ring)
= 2 (V
T+(max)
(R1 + R3 + R4) / R4 + 0.7)
Tolerance to noise between Tip and Ring and VSS is:
Vpeak
(max noise)
= V
T+(min)
(R1 + R3 + R4) / R4 + 0.7
Time constant is:
T = R5 C3 ln [VDD / (VDD - V
T+
)]
V
T+(min)
<= V
T+
<= V
T+(max)
R5 from 10K ohm to 500K ohm.
C3 from 47 nF to 0.68 uF.
Figure 6-18 Application Circuit of the Ring Detector
The RC time constant of the RNGRC pin is used to delayed the output pulse of the RNG flag for a
low going edge on RNGDI. This edge goes from above the V
T+
voltage to the Schmitt trigger low
going threshold voltage V
T-
. The RC time constant must be greater than the maximum period of
the ring signal, to ensures a minimum RNG high interval and to filter the ring signal to get an
envelope output. The rising signal of RNG will set the bit RNGF(CIDFG.0) high to cause the CID
flag(CIDF) high.
The diode bridge shown in Figure 6-18 works for both single ended ring signal and balanced
ringing. The R1 and R2 are used to set the maximum loading and must be of equal value to
achieve balanced loading at both the tip and ring line. R1, R3 and R4 form a resistor divider to
supply a reduced voltage to the RNGDI input. The attenuation value is determined by the
detection of minimal ring voltage and maximum noise tolerance between tip/ring and ground.
Input Pre-Processor
The input signal is processed by Input Pre-Processor, which is comprised of two OP amps and a
bias source(VREF). The gain OP-amps are used to bias the input voltage with the VREF signal
voltage. VREF is V
AD
/2 typically, this pin is recommended to connect a 0.1 uF capacitor to V
AS
.
The gain adjustable OP amps are sued to select the input gain by connecting a feedback resistor
between GCFB and INN pins. Figure 6-19 shows the differential input configuration and Figure
6-20 shows the single-ended configuration.
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