參數(shù)資料
型號: W925E625
英文描述: Telephone Controller
中文描述: 電話控制器
文件頁數(shù): 40/71頁
文件大?。?/td> 1055K
代理商: W925E625
W925E/C625
8-bit CID Microcontroller
In Mode 0, the timer/counters act as 13-bit timer/counters. The 13 bits consist of 8 bits of THx and
lower 5 bits of TLx. The upper 3 bits of TLx are ignored.
The negative edge of the clock causes the content of the TLx register to increase one. When the
fifth bit in TLx moves from 1 to 0, then the count in the THx register is incremented. When the
count in THx moves from FFh to 00h, then the overflow flag TFx is set. The counted input is
enabled only if TRx is set and either GATE=0 or
INTx
=1. When C/
T
is set to 0, then it will count
clock cycles, and if C/T is set to 1, then it will count 1 to 0 transitions on T0 (P3.4) for timer 0 and
T1 (P3.5) for timer 1. When the 13-bit count reaches 1FFFh, the next count will cause it to rollover
to 0000h. The timer overflow flag TFx of the relevant timer is set and if enabled an interrupts will
occur. Note that when they are used as a timer, the bits of the CKCON1 select the time-base.
MODE1
Mode 1 is similar to Mode 0 except that the counting register forms a 16-bit counter, rather than a
13 bit counter.
Revision : A6
-40-
Release Date : 2002/7/2
C/T = TMOD.2
(C/T = TMOD.6)
0
M1,M0 = TMOD.1,TMOD.0
(M1,M0 = TMOD.5,TMOD.4)
Interrupt
T0 = P3.4
(T1 = P3.5)
TH0
(TH1)
TL0
(TL1)
TF0
(TF1)
TR0 = TCON.4
(TR1 = TCON.6)
GATE = TMOD.3
(GATE = TMOD.7)
INT0 = P3.2
(INT1 = P3.3)
PS: Functions of timer1 are shown in brackets
7
0
TFx
4
7
0
00
1
01
TM0=CKCON1.2, CKCON1.3
(TM1=CKCON1.4, CKCON1.5)
mux
00
01
10
11
Fosc/4
Fosc/64
Fosc/1024
Fs
Figure 6-5 Mode 0 & Mode 1 of Timer/Counter 0 & 1
MODE 2
Mode 2 is the Auto Reload Mode. In mode 2, TLx acts as an 8-bit count register, while THx holds
the reload value. When the TLx register overflows from FFh to 00h, the TFx bit is set and TLx is
reloaded with the content of THx, and the counting process continues from the reloaded TLx. The
reload operation leaves the content of the THx register unchanged. Counting is controlled by the
TRx bit and the proper setting of GATE and INTx pins.
BUZZER
In mode 2, timer 0 can be use to output an arbitrary frequency to the BUZ pin by programming
bit6 and bit7 of CKCON2. BUZ pin can be configured as key tone (KT) output by setting BUZSL
to high. When disable buzzer output by clearing ENBUZ to low, the BUZ output is in floating
status.
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