
W925E/C625
8-bit CID Microcontroller
6.13 I/O Ports
Revision : A6
-48-
Release Date : 2002/7/2
There are six 8-bit ports named from P0 to P4 in W925E/C625. All ports can be configured as
input or output mode. Except P0, every port has pull high resistor enable/disable by PxH register.
After reset the initial state of each port is in input mode and the value of the registers from P0 to
P3 are FFh. The I/O port is described as below:
P0
: I/O mode is controlled by P0IO. Only
P0 output as open drain mode
and without pull high
resistor.
P1
: I/O mode is controlled by P1IO. Pull high is controlled by P1H.
P1.0~P1.3 work as INT2
,
P1.4~P1.7 work as INT3
.
Falling edge
on P1 pins to produce INT2 and INT3 flag.
P1 is
configured as INT2/INT3 by P1EF register.
P2
: I/O mode is controlled by P2IO. Pull high is controlled by P2H.
P3
: I/O mode is controlled by P3IO. Pull high is controlled by P3H.
P3.5
T1
Timer/counter 1 external count input
P3.4
T0
Timer/counter 0 external count input
P3.3
INT1
External interrupt 1
P3.2
INT0
External interrupt 0
P4
: I/O mode is controlled by P4IO. Pull high is controlled by P4H.
Special function of P4 is described below.
P4.4
Vpos
Positive input of the comparator
P4.2
Vneg
Negative input of the comparator
P4.1
SDATA
Serial port output
P4.0
SCLK
Serial port input
6.14 Divider
A built-in 13/14-bit binary up-counter designed to generate periodic interrupt. The clock source is
from sub-oscillator. When the frequency of sub-crystal is 32768Hz, it provides the divider interrupt
in the period of 0.25/0.5 second. Bit DIVS controls the degree of divider. When DIVA is high to
enable the divided counter, when DIVA is low to reset divider and stop counting. As the divider
overflows, the divider interrupt flag DIVF is set. DIVF is clear by software or serving divider
interrupt routine.
13
14
1
overflow
DIVF
(EXIF.3)
DIVS
(CKCON1.1)
DIVA
(DIVC.0)
Fs
ck
D
Q
CR
Executing DIV Int
Clear by software
Figure 6-13 13/14-bit Divider
6.15 LCD
1792 dots: 56 Segments x 32 Common, 1/5 bias