- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄202451 > VG36128161BFL-7L (VANGUARD INTERNATIONAL SEMICONDUCTOR CORP) 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54 PDF資料下載
參數(shù)資料
| 型號(hào)： | VG36128161BFL-7L |
| 廠商： | VANGUARD INTERNATIONAL SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54 |
| 封裝： | 10 X 9 MM, VFBGA-54 |
| 文件頁數(shù)： | 6/69頁 |
| 文件大?。?/td> | 1335K |
| 代理商： | VG36128161BFL-7L |
第1頁第2頁第3頁第4頁第5頁當(dāng)前第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁
Document :1G5-0183
Rev.5
Page 14
VIS
VG36128401B / VG36128801B / VG36128161B
CMOS Synchronous Dynamic RAM
2.5 Command Truth Table for CKE (Note 1)
Note:
Current state
CKE
n - 1
CKE
n
CS
RAS
CAS
WE
Address
Action
Notes
Self refresh
(S.R.)
H
X
INVALID, CLK (n - 1)would exit S.R.
L
H
X
S.R. Recovery
2
L
H
L
H
X
S.R. Recovery
2
L
H
L
H
L
X
ILLEGAL
L
H
L
X
ILLEGAL
L
X
Maintain S.R.
Self refresh
recovery
H
X
Idle after tRC
H
L
H
X
Idle after tRC
H
L
H
L
X
ILLEGAL
H
L
X
ILLEGAL
H
L
H
X
Begin clock suspend next cycle
5
H
L
H
X
Begin clock suspend next cycle
5
H
L
H
L
X
ILLEGAL
H
L
X
ILLEGAL
L
H
X
Exit clock suspend next cycle
2
L
X
Maintain clock suspend
Power down
(P.D.)
H
X
INVALID, CLK (n - 1) would exit P.D.
L
H
X
EXIT P.D.
Idle
2
L
X
Maintain power down mode
Both banks
idle
H
X
Refer to operations in Operative
Command Table
H
L
H
X
Refer to operations in Operative
Command Table
H
L
H
X
Refer to operation in Operative
Command Table
H
L
H
X
Auto Refresh
H
L
Op - Code Refer to operations in Operative
Command Table
H
L
H
X
Refer to operations in Operative
Command Table
H
L
H
X
Refer to operations in Operative
Command Table
H
L
H
X
Refer to operations in Operative
Command Table
H
L
H
X
Self refresh
3
H
L
Op - Code Refer to operations in Operative
Command Table
L
X
Power down
3
Any state
other than
listed above
H
X
Refer to operations in Operative
Command Table
H
L
X
Begin clock suspend next cycle
4
L
H
X
Exit clock suspend next cycle
L
X
Maintain clock suspend
1. H : Hight level, L : low level, X : High or low level (Don't care).
2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup
time must be satisfied before any command other than EXIT.
3. Power down and Self refresh can be entered only from the both banks idle state.
4. Must be legal command as defined in Operative Command Table.
5. Illegal if tSREX is not satisfied.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VG95234E32-5P1X | 2 CONTACT(S), ALUMINUM ALLOY, MALE, MIL SERIES CONNECTOR, CLAMP AND CRIMP, PLUG |
| VG95234E32-5P1Y | 2 CONTACT(S), ALUMINUM ALLOY, MALE, MIL SERIES CONNECTOR, CLAMP AND CRIMP, PLUG |
| VG95234E32-5P1Z | 2 CONTACT(S), ALUMINUM ALLOY, MALE, MIL SERIES CONNECTOR, CLAMP AND CRIMP, PLUG |
| VG95234E32-5PN | 2 CONTACT(S), ALUMINUM ALLOY, MALE, MIL SERIES CONNECTOR, CLAMP AND CRIMP, PLUG |
| VG95234E32-5PW | 2 CONTACT(S), ALUMINUM ALLOY, MALE, MIL SERIES CONNECTOR, CLAMP AND CRIMP, PLUG |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VG36128161BT | 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM |
| VG36128401A | 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM |
| VG36128401BT | 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM |
| VG36128801A | 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM |
| VG36128801BT | 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。