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參數(shù)資料
| 型號(hào)： | VG36128161BFL-7L |
| 廠商： | VANGUARD INTERNATIONAL SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54 |
| 封裝： | 10 X 9 MM, VFBGA-54 |
| 文件頁數(shù)： | 11/69頁 |
| 文件大?。?/td> | 1335K |
| 代理商： | VG36128161BFL-7L |
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Document :1G5-0183
Rev.5
Page 19
VIS
VG36128401B / VG36128801B / VG36128161B
CMOS Synchronous Dynamic RAM
8. Auto Precharge
During a read or write command cycle, A10 controls whether auto precharge is selected. If A10 is high in the read or write
command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is selected and
begins automatically.
In the write cycle, tDAL(min.) must be satisfied before asserting the next activate command to the bank being precharged.
When using auto precharge in the read cycle, knowing when the precharge starts is important because the next activate
command to the bank being precharged cannot be executed until the precharge cycle ends. Once auto precharge has
started, an activate command to the bank can be asserted after tRP has been satisfied.
A Read or Write command without auto - precharge can be terminated in the midst of a burst operation. However, a Read
or Write command with auto - precharge can not be interrupted by the same bank commands before the entire burst opera-
tion is completed. Therefore use of the same bank Read, Write, Precharge or Burst Stop command is prohibited during a
read or write cycle with auto - precharge. It should be noted that the device will not respond to the Auto - Precharge com-
mand if the device is programmed for full page burst read or write cycles.
The timing when the auto precharge cycle begins depends both on both the CAS Iatency programmed into the mode reg-
ister and whether the cycle is read or write.
8.1 Read with Auto Precharge
During a READA cycle, the auto precharge begins one clock earlier (CL = 2) or two clocks earlier (CL = 3) than the last
word output.
READ with AUTO PRECHARGE
Burst lengh = 4
CLK
Command
CAS latency = 2
DQ
Command
CAS latency = 3
DQ
Remark READA means READ with AUTO PRECHARGE
Hi - Z
Auto precharge starts
QB0
QB3
QB2
QB1
READA B
T0
T1
T2
T3
T4
T5
T6
T7
Auto precharge starts
Hi - Z
T8
QB0
QB3
QB2
QB1
No New Command to Bank B
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VG36128161BT | 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM |
| VG36128401A | 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM |
| VG36128401BT | 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM |
| VG36128801A | 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM |
| VG36128801BT | 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM |
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