參數(shù)資料
型號: VDP3130Y
廠商: MICRONAS SEMICONDUCTOR HOLDING AG
英文描述: Video Processor Family
中文描述: 視頻處理器系列
文件頁數(shù): 47/76頁
文件大小: 1770K
代理商: VDP3130Y
ADVANCE INFORMATION
VDP 313xY
Micronas
47
171
bit[11:0]
first line of macrovision detection window
(relative to vsync)
6
MCV_START
172
bit[11:0]
last line of macrovision detection window
(relative to vsync)
15
MCV_STOP
Scaler Control Register
40
scaler mode register
bit[1:0]
scaler mode
0
1
2
3
linear scaling mode
nonlinear scaling mode,
panorama
nonlinear scaling mode,
waterglass
reserved
bit[10:2]
reserved, set to 0
bit[11]
scaler update
0
start scaler update command,
when the registers are updated the bit is set
to 1
0
SCMODE
MODE
SCUP
41
luma offset register
bit[6:0]
luma offset 0..127
ITU-R output format:
CVBS output format:
57
4
this register is updated when the scaler mode register is written
57
YOFFS
42
active video length for 1-h FIFO
bit[11:0]
length in pixels
this register is updated when the scaler mode register is written
1080
FFLIM
43
scaler1 coefficient, this scaler is compressing the signal.
For compression by a factor c the value c*1024 is required.
bit[11:0]
allowed values from 1024..4095
this register is updated when the scaler mode register is written
1024
SCINC1
44
scaler2 coefficient, this scaler is expanding the signal.
For expansion by a factor c the value 1/c*1024 is required.
bit[11:0]
allowed values from 256..1024
this register is updated when the scaler mode register is written
1024
SCINC2
45
scaler1/2 nonlinear scaling coefficient
this register is updated when the scaler mode register is written
0
SCINC
47 -
4B
scaler1 window controls, see table
5 12-bit registers for control of the nonlinear scaling
this register is updated when the scaler mode register is written
0
SCW1_0 - 4
Table 2
6:
Control Registers of the Fast Processor for control of the video frontend functions
default values are initializied at reset
FP Sub-
address
(hex)
Function
Default
Name
(hex)
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