
ADVANCE INFORMATION
VDP 313xY
Micronas
29
2.14.Serial Interface
2.14.1.I
2
C-Bus Interface
Communication between the VDP and the external
controller is done via I
2
C-bus. The VDP has two
I
2
C-bus slave interfaces (for compatibility with VPC/
DDP applications) - one in the front-end and one in the
back-end. Both I
2
C-bus interfaces use I
2
C clock syn-
chronization to slow down the interface if required.
Both I
2
C-bus interfaces use one level of subaddress:
the I
2
C-bus chip address is used to address the IC and
a subaddress selects one of the internal registers. The
I
2
C-bus chip addresses are given below:
The registers of the VDP have 8 or 16-bit data size;
16-bit registers are accessed by reading/writing two
8-bit data words.
Fig. 2
–
27 shows I
2
C-bus protocols for read and write
operations of the interface; the read operation requires
an extra start condition and repetition of the chip
address with read command set.
Fig. 2
–
27:
I
2
C-bus protocols
Table 2
–
3:
I
2
C Chip Addresses
Chip
Address
A6
A5
A4
A3
A2
A1
A0
R/W
front-end
1
0
0
0
1
1
1
1/0
back-end
1
0
0
0
1
0
1
1/0
P
S
1
0
SDA
SCL
S
S
1000 111
1000 111
W Ack
Ack
W
0111 1100
0111 1100
Ack
Ack
S
1 or 2 byte Data
1000 111
R
high byte Data
low byte Data
P
W
R
Ack
Nak
S
P
=
=
=
=
=
=
0
1
0
1
Start
Stop
Ack
Nak P
I
2
C write access
subaddress 7c
I
2
C read access
subaddress 7c
Ack
S
1000 111
W Ack
FPWR
Ack
P
byte high
send FP-address-
Ack
byte low
send FP-address-
Ack
S
1000 111
W Ack
FPDAT
Ack
P
byte high
send data-
Ack
byte low
send data-
Ack
I
2
C write access
to FP
S
1000 111
W Ack
FPRD
Ack
P
byte high
send FP-address-
Ack
byte low
send FP-address-
Ack
S
1000 111
W Ack
FPDAT
Ack
P
byte high
receive data-
receive data-
Ack
byte low
Nak
I
2
C read access
to FP
S
1000 111
R Ack