VDSL5100
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MII/SMII/SS-SMII/RMII
compliant with the 802.3 Ethernet
specification
P
R O D U C T
B
R I E F
N e v e r s t o p t h i n k i n g .
V D S L 5 1 0 0
5th Generation Single-port Standard VDSL Chip Set
VDSL5100-D, PEF 22818
4bVDSL-A, PEF 22815
VDSL-L, PEF 22810
Applications
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Customer Premises Equipment
(CPE)
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DSLAM and residential gateways
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Ethernet and ATM over VDSL for
last mile access solutions
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Fiber and broadband wireless
extension over copper wire
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Multiple Dwelling/Tenant Units
(MDU/MTU) networking
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LAN extentsions up to 1,200 m
(4,000 ft.)
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Upgrades of HDSL, SDSL and
ADSL systems
Features
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Ethernet and ATM single port chip
set
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Highly integrated, standard
compliant, VDSL QAM transport
modem
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Low power consumption
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T1E1.4, ETSI, and ITU-T
compliant high speed VDSL PHY
applications
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Ethernet transfer over AAL5 and
RFC 2684
Infineon’s VDSL5100 standard VDSL single port
chip set provides highly flexible solutions for
Ethernet and ATM applications over VDSL.
Access system designers’ requirements are
addressed by providing flexible band allocation
plans and PSDs. VDSL5100 also supports Band 0
to extend VDSL services up to 4 km (13,200 ft.)
over ADSL frequencies.
Infineon’s VDSL5100 chip set uses Frequency
Division Multiplexing (FDM) and Quadrature
Amplitude Modulation (QAM) to provide simple,
low-cost, low-power, and very robust operation.
Infineon’s VDSL5100 is designed to coexist with
voice, ISDN, and other xDSL technologies in the
same bundle.
With Infineon’s software configurable VDSL5100
chip set, system vendors can use a single design
to support a wide variety of transport protocols.
The VDSL5100 is ideal for universal DSLAM
linecards and CPE designs.
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Frequency Division Duplexing
(FDD)
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2, 3, or 4-band operation,
including Band 0
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Dual latency support with built-in
interleaver memory
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Power Back Off
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Embedded crystal oscillator
(DCXO) for timing recovery
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Spectral allocation allows noise
free operation with xDSL, ISDN,
TCM-ISDN and digital PBX
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Versatile and completely flexible
band allocations
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Backward compatibility with
Infineon’s legacy chip sets
Performance
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Asymmetric DS/US data rates of
70/40 Mbit/s and Symmetric data
rates up to 50 Mbit/s
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Asymmetric DS/US data rates of
4/0.6 Mbit/s up to 4 km (13,200 ft.)
Interfaces
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ATM UTOPIA Level 1 and
Level 2, 8-bit, 33 MHz
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32-channel Pulse Code
Modulation (PCM), maximum
2 Mbit/s over the fast channel
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MII serial management interface
to access all internal registers
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External parallel host port
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Serial UART interface to a
standard serial terminal
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EEPROM interface via IIC
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IEEE 1149.1 JTAG test port
Power Requirements
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3.3 V and 1.2 V for the PEF 22818
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1.8 V for the PEF 22815
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±5 V for the PEF 22810