參數(shù)資料
型號(hào): VDP3130Y
廠商: MICRONAS SEMICONDUCTOR HOLDING AG
英文描述: Video Processor Family
中文描述: 視頻處理器系列
文件頁數(shù): 39/76頁
文件大?。?/td> 1770K
代理商: VDP3130Y
ADVANCE INFORMATION
VDP 313xY
Micronas
39
Analog RGB Insertion
4B
9
w v
bit[7]
0/1
disable/enable analog fast blank
input for RGB inserion
0
ERGB
4B
9
w v
bit[0]
0
1
Picture frame overOSD
OSD over picture frame
0
OSDPRIO
32
8
w/r
fast blank interface mode
bit[0]
0
internal fast blank 1 from FBLIN1
pin
force internal fast blank 1 signal
to high
internal fast blank active high/low
disable/enable clamping
reference for RGB outputs
full line MADC measurement
window, disables bit [3] in
address 25
horizontal flyback input active
high/low
reserved (set to 0)
internal fast blank 1 from FBLIN1
pin
force internal fast blank 1 signal
to low
1
bit[1]
bit[2]
0/1
0/1
bit[3]
1
bit[4]
0/1
bit[6:5]
bit[7]
0
1
0
FBMOD
FBFOH1
FBPOL
CLMPR
FLMW
FLPOL
FBFOL1
31
8
w/r
fast blank interface mode 2
bit[0]
0
internal fast blank 2 from FBLIN2
pin
force internal fast blank 2 signal
to high
internal fast blank 2 from FBLIN2
pin
force internal fast blank 2signal to
low
fast blank input priority
0
FBLIN1>FBLIN2
1
FBLIN2>FBLIN1
fast blank monitor input select
0
monitor connected to FBLIN1 pin
1
monitor connected to FBLIN2 pin
half contrast switch enable
0/1
HCS disable/enable
0
half contrast from HCS pin
1
force half contrast signal to high
0/1
half contrast active high/low at
HCS pin
reserved (set to 0)
1
bit[1]
0
1
bit[2]
bit[3]
bit[4]
bit[5]
bit[6]
bit[7]
0
FBMOD2
FBFOH2
FBFOL2
FBPRIO
FBMON
HCSEN
HCSFOH
HCSPOL
Table 2
5:
I
2
C control and status registers of the video backend
(Registers are set to
0
at reset, default values are recommendations)
I
2
C Sub
address
(hex)
Number
of bits
Mode
Function
Default
Name
(hex)
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