參數(shù)資料
型號(hào)： VDP3108
廠(chǎng)商： MICRONAS SEMICONDUCTOR HOLDING AG
英文描述： Single-Chip Video Processor
中文描述： 單芯片視頻處理器
文件頁(yè)數(shù)： 22/61頁(yè)
文件大小： 2638K
代理商： VDP3108
VDP 3108
ADVANCE INFORMATION
MICRONAS INTERMETALL
22
2.6.3. Vertical, East–West Deflection
The calculations of the vertical and east–west deflection
waveforms are done by the fast processor. The algo-
rithm is using a chain of accumulators to generate the re-
quired polynomial waveforms. To produce the deflection
waveforms, the accumulators are initialized at the begin-
ning of each field. The initialization values must be com-
puted by the control processor and are written once to
the fast processor of the VDP3108. The waveforms are
described as polynomials in x, where x varies from 0 to
1 for one field.
P: a+ b(x–0.5) + c(x–0.5)
2
+
d(x–0.5)
3
+ e(x–0.5)
4
The initialization values for the accumulators a0..a3 for
vertical deflection and a0..a4 for east–west deflection
are 12 bit values. The coefficients that should be used
to calculate the initialization values for different field fre-
quencies are given is section 3.
The vertical waveform can be scaled according the aver-
age beam current. This is used to compensate the ef-
fects of electric high tension changing due to beam cur-
rent variations. In order to get a faster vertical retrace
timing, the output impedance of the vertical DA convert-
er can be reduced by 50% during the retrace.
Fig. 2–29 shows some vertical and east–west deflection
waveforms. The polynomial coefficients are given in the
figure.
Fig. 2–29:
Vertical and East–West Deflection Waveforms
vertical: a,b,c,d 0,1,0,0
east–west: a,b,c,d,e
0,0,1,0,0
0,0,0,0,1
0,0,1,1,1
0,1,1,0
0,1,0,1
2.6.4. Protection Circuitry
Picture tube and drive stage protection is provided
through the following measures:
– vertical flyback safety input: this pin looks for a nega-
tive edge in every field, otherwise the RGB drive sig-
nals are blanked.
– drive shutoff during flyback: this feature can be se-
lected by software.
– safety input pin: this pin has two thresholds; at the low-
er threshold the RGB signals are blanked, at the high-
er threshold the horizontal drive is shut off.
– The main oscillator and the horizontal drive circuitry
are run from a separate (standby) power supply and
are already active while the TV set is powering up.
2.7. Reset and Standby Functions
Reset of most functions (exceptions see below) is per-
formed by a reset pin. When this pin becomes active
then all the internal registers and counters are set to
zero. When this pin is released, the internal reset is still
active for 4us. After that time all the internal registers are
loaded with the values defined in the defaults ROM. All
the registers which are updated with the vertical sync
get these values with the next vertical sync. During this
initialization procedure (approx. 60
μ
s) it is not possible
to access the VDP via the serial interface (I
2
C). Access
to other ICs via the serial bus is possible during that time.
The same initialization procedure is started when the in-
ternal clock supervision detects that there is no clock (in
the video processing part).
Exceptions for initialization :
– CCU clock divider (5MHz), not initialized by reset
– standby clock divider (1MHz), not initialized by reset,
but clock selector switched to standby clock
During standby, only the horizontal drive pulse (see also
2.6.2.) and the 5 MHz clock output for the control micro-
processor are active. The standby circuitry is reset when
the standby supply voltage is applied.
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