參數(shù)資料
型號(hào)： VDP3108
廠商： MICRONAS SEMICONDUCTOR HOLDING AG
英文描述： Single-Chip Video Processor
中文描述： 單芯片視頻處理器
文件頁(yè)數(shù)： 21/61頁(yè)
文件大小： 2638K
代理商： VDP3108
ADVANCE INFORMATION
VDP 3108
MICRONAS INTERMETALL
21
2.6.2. Deflection Processing
The deflection processing generates the signals for the
horizontal and vertical drive (fig. 2–27). This block con-
tains two phase-locked loops:
– PLL2 generates the horizontal and vertical timing.
Phase and frequency are synchronized by the front
sync signal. The Main Sync (MSY) signal that is gener-
ated from PLL2 is a multiplex of all display related data
(fig. 2–28). This signal is intended for use by other pro-
cessors, e.g. a PIP processor can use this signal to ad-
just to a certain display position.
– PLL3 adjusts the phase of the horizontal drive pulse
and compensates for the delay of the horizontal output
stage.
The horizontal drive circuitry uses a digital sine wave
generator to produce the exact (subclock) timing for the
drive pulse. The generator runs at 1 MHz; in the output
stage the frequency is divided down to give drive-pulse
period and width. In standby mode, the output stage is
driven from an internal 1 MHz clock that is derived from
the 20 MHz main clock oscillator and a fixed drive pulse
width is used. When the circuit is switched out of standby
operation the drive pulse width is programmable. The
horizontal drive uses a high voltage (8V) open drain out-
put transistor.
phase
comparator
&
lowpass
PLL2
composite
sync
generator
E/W
correction
sawtooth
PWM
15 bit
CSY
E/W
ouput
V
output
V
flyback
PWM
15 bit
DCO
main
sync
interface
FSY
VDATA
main
sync
generator
vertical
serial
data
phase
comparator
&
lowpass
PLL3
1:64
&
output
stage
H
flyback
H
drive
DCO
display
timing
line
counter
blanking, clamping, etc.
clock & control
sinewave
generator
&
DAC
LPF
Standby clock
Fig. 2–27:
Deflection processing block diagram
MSY
M1
M2
(not in scale)
M1
M2
F
V
l[0]
l[7]
l[8]
not
Parity
input
analog
video
MSY
not
not
not
not
timing reference for PICTURE bus
– chroma multiplex sync
– active picture data after xxx clocks
V:
Vert. blanking
0 = off
1 = on
Field #
0 = Field 1
1 = Field 2
line: Field line #
1...N
F:
Parity
Fig. 2–28:
Main sync format
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