參數(shù)資料
型號： V54C316162VB
廠商： Mosel Vitelic, Corp.
英文描述： High Performance 3.3 Volt 1M X 16 Synchronous DRAM(3.3V高性能1Mx16同步動態(tài)RAM)
中文描述： 高性能3.3伏100萬× 16同步DRAM（3.3V的高性能1Mx16同步動態(tài)RAM）的
文件頁數(shù)： 7/61頁
文件大?。?/td> 571K
代理商： V54C316162VB
MOSEL V ITELIC
V54C316162VB
7
V54C316162VB Rev. 1.0 July 1998
Read and Write Access Mode
When RAS is low and both CAS and WE are
high at the positive edge of the clock, a RAS cycle
starts. According to address data, a word line of
the selected bank is activated and all of sense am-
plifiers associated to the word line are fired. A CAS
cycle is triggered by setting RAS high and CAS low
at a clock timing after a necessary delay, tRCD,
from the RAS timing. WE is used to define either a
read (WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access
modes. In a single CAS cycle, serial data read or
write operations are allowed at up to a 125 MHz
data rate. The numbers of serial data bits are the
burst length programmed at the mode set opera-
tion, i.e., one of 1, 2, 4, 8 and full page. Column ad-
dresses are segmented by the burst length and
serial data accesses are done within this boundary.
The first column address to be accessed is supplied
at the CAS timing and the subsequent addresses
are generated automatically by the programmed
burst length and its sequence. For example, in a
burst length of 8 with interleave sequence, if the first
address is ‘2’, then the rest of the burst sequence is
3, 0, 1, 6, 7, 4, and 5 .
Similar to the page mode of conventional
DRAM’s, burst read or write accesses on any col-
umn address are possible once the RAS cycle
latches sense amplifiers. The maximum tRAS or the
refresh interval time limits the number of random
column accesses. A new burst access can be done
even before the previous burst ends. The interrupt
operation at every clock cycles is supported. When
the previous burst is interrupted, the remaining ad-
dresses are overridden by the new address with the
full burst length. An interrupt which accompanies
with an operation change from a read to a write is
possible by exploiting DQM to avoid bus contention.
When two banks are activated sequentially, inter-
leaved bank read or write operations are possible.
With the programmed burst length, alternate access
and precharge operations on two banks can realize
fast serial data access modes among many differ-
ent pages. Once two banks are activated, column to
column interleave operation can be done between
two different pages.
Refresh Mode
SDRAM has two refresh modes, a CAS before
RAS (CBR) automatic refresh and a self refresh. All
of banks must be precharged before applying any
refresh mode. An on-chip address counter incre-
ments the word and the bank addresses and no
bank information is required for both refresh modes.
The chip enters the automatic refresh mode,
when RAS and CAS are held low and CKE and WE
are held high at a clock timing. The mode restores
word line after the refresh and no external pre-
charge command is necessary. A minimum tRC
time is required between two automatic refreshes in
a burst refresh mode. The same rule applies to any
access command after the automatic refresh oper-
ation.
The chip has an on-chip timer and the self re-
fresh mode is available. It enters the mode when
RAS, CAS, and CKE are low and WE is high at a
clock timing. All of external control signals includ-
ing the clock are disabled. Returning CKE to high
enables the clock and initiates the refresh exit op-
eration. After the exit command, at least one tRC
delay is required prior to any access command.
DQM Function
DQM has two functions for data I/O read write op-
erations. During reads, when it turns to high at a
clock timing, data outputs are disabled and become
high impedance after two clock delay (DQM Data
Disable Latency t
DQZ
). It also provides a data mask
function for writes. When DQM is activated, the
write operation at the next clock is prohibited (DQM
Write Mask Latency t
DQW
= zero clocks).
Suspend Mode
During normal access mode, CKE is held high
and CLK is enabled. When CKE is low, it freezes
the internal clock and extends data read and write
operations. One clock delay is required for mode
entry and exit (Clock Suspend Latency t
CSL
).
Power Down
In order to reduce standby power consumption, a
power down mode is available. Bringing CKE low
enters the power down mode and all of receiver cir-
cuits are gated. All banks must be precharged be-
fore entering this mode. One clock delay is required
for mode entry and exit. The Power Down mode
does not perform any refresh operation.
Auto Precharge
Two methods are available to precharge
SDRAMs. In an automatic precharge mode, the
CAS timing accepts one extra address, CA10, to
determine whether the chip restores or not after the
operation. If CA10 is high when a Read Command
is issued, the
Read with Auto-Precharge
is initiated. The SDRAM automatically enters the
precharge operation one clock after the Read Com-
mand is registered for CAS latencies of 1 and 2, and
function
相關(guān)PDF資料
PDF描述
V54C316162 200/183/166/143 MHz 3.3 VOLT, 4K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16
V54C316162VC-5 200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16
V54C316162VC-55 200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16
V54C316162VC-6 200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16
V54C316162VC-7 200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
V54C316162VC 制造商:MOSEL 制造商全稱:MOSEL 功能描述:200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16
V54C316162VC-5 制造商:MOSEL 制造商全稱:MOSEL 功能描述:200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16
V54C316162VC-55 制造商:MOSEL 制造商全稱:MOSEL 功能描述:200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16
V54C316162VC-6 制造商:MOSEL 制造商全稱:MOSEL 功能描述:200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16
V54C316162VC-7 制造商:MOSEL 制造商全稱:MOSEL 功能描述:200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16
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