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參數(shù)資料
| 型號(hào)： | UC1602I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 65x102 Matrix LCD Controller-Driver |
| 中文描述： | 65x102矩陣LCD控制器驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 26/38頁 |
| 文件大小： | 723K |
| 代理商： | UC1602I |
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U
LTRA
C
HIP
High-Voltage Mixed-Signal IC
2000
24
Product Specifications
P
REPARE
T
O
A
CCESS
D
ATA
RAM
Address control (register AC) flags and some LCD to SRAM mapping (register LC) flags affect how data is
stored into the display buffer SRAM => Make proper adjustment to these two registers before writing data to
UC1602I display buffer SRAM.
These sequence can be performed in parallel 8-bit, I
2
C or S8 modes. These commands can be performed
under any operating mode (OM).
# C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
0
0
1
0
0
0
1
1
Operation
OM
–
–
BZ
0
0
Comments
0
0
0
0
1
#
#
#
#
0
# (Opt.) Set Address Control
# (Opt.) Set/clear LCD
Mapping control flags.
D
ATA
RAM A
CCESS
: W
RITE
These sequence can be performed in parallel 8-bit, I
2
C or S8. These commands can be performed under
any operating mode (OM).
# C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
1
0
2
0
0
0
0
3
0
0
0
0
4
1
0
#
#
Operation
OM
–
–
–
–
BZ
0
0
0
0
Comments
1
0
0
#
1
1
0
#
#
#
#
#
#
#
#
#
#
#
#
#
# Set Page Address
# Set Column Address MSB
# Set Column Address LSB
# Write Display Data
(repeat as appropriate)
(Return to 1 as necessary,
repeat until complete)
5
–
0
D
ATA
RAM A
CCESS
: R
EAD
For parallel interface and I
2
C modes, a dummy Read cycle is required when a Read Data command follows
immediately after a Write cycle (either Write Data or Write Control).
# C/D W/R D7 D6 D5 D4 D3 D2 D1 D0
1
X
0
1
0
Operation
OM
–
BZ
0
Comments
For example:
Commands setting
PA and/or CA.
1
1
#
#
#
# Write cycle
(either data or control)
2
3
1
1
1
1
–
#
–
#
–
#
–
#
–
#
–
#
–
#
– Dummy Read cycle
# Read Display Data
(repeat as appropriate)
–
–
0
0
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