
UC1602I
65x102 Matrix LCD Controller-Drivers
Rev. 0.54 10/12/2001
15
2-
WIRE INTERFACE TIMING
The 2-wire I
2
C interface is a bidirectional
interface. In order to properly communicate
between all I
C devices, certain timing protocols
need to be satisfied.
There are always master and slave devices on
an I
C bus. The master device initiates an read or
write action to the slave device with an address.
The selected slave device to the action
transimitting or receiving data. Without any action,
the I
C bus are pulled high by two pull-up
resistors. A master or slave device initiates or
responds to an action by pulling down the bus.
UC1602I is a slave I
C device.
In idle mode, the both wires, SDA and SCK are
pulled high. When the SDA makes a HIGH to
LOW transition while SCK remains high, this is
the I
C START condition. When the SDA makes
a LOW to HIGH transition while SCK remain low,
this is I
C STOP condition. In between a START
and STOP condition, I
C transmits data bits by
toggling SCK while SDA remains stable. These
relations are shown in
Figure 8
.
Figure 8
. I
2
C bus SDA and SCK timing relation.
Each eight-bit of data is followed by an
acknowledge pulse from the receiver as shown in
Figure
9
. The master device will generate an
extra pulse during this time. It is the receiving
device’s responsibility to generate this
acknowledge pulse regardless of being a master
or slave device. UC1602I generates an
acknowledge pulse in the write mode. When the
acknowledge pulse is HIGH, UC1602I has
received write instruction or data correctly. When
the acknowledge pulse is LOW, UC1602I has not
correctly received instruction and the master
device needs to resend.
Figure 9
. I
2
C bus acknowledge pulse
SDA
SCK
STOP
START
DATA 1
DATA 1
DATA 0
SCK
Data
Transmitter
Data
Receiver
S
1
2
3
8
9
No-Acknowledge
Acknowledge