
UC1602I
65x102 Matrix LCD Controller-Drivers
Rev. 0.54 10/12/2001
17
D
ISPLAY
D
ATA
RAM
D
ATA
O
RGANIZATION
The display data is one bit per pixel and stored in
a dual port static RAM (RAM, for Display Data
RAM). The RAM size is 65x102. This array of
data bits are further organized into pages of 8 bit
slices to facilitate parallel bus interface.
At the end of the graphics data, UC1602I
contains an 1-bit wide page for icon data.
When Mirror X (MX, LC[2]) is OFF, the 1
st
column
of LCD pixels will correspond to the bits of the
first byte of each page, the 2
column of LCD
pixels correspond to the bits of the second byte
of each page, etc.
MSB F
IRST OR
LSB F
IRST
There are two options to map D[7:0] to RAM,
MSB first (MSF=1), or LSB first (MSF=0), as
illustrated below.
D
ISPLAY
D
ATA
RAM A
CCESS
The memory used in UC1602I Display Data RAM
(RAM) is a special purpose two port SRAM which
allows asynchronous access to both its column
and row data. Thus, RAM can be independently
accessed both for Host Interface and for display
operations.
D
ISPLAY
D
ATA
RAM A
DDRESSING
A Host Interface (HI) memory access operation
starts with specifying Page Address (PA) and
Column Address (CA) by issuing
Set Page
Address
and
Set Column Address
commands.
If wrap-around (WA, AC[0]) is OFF (0), CA will
stop incrementing after reaching the end of page
(102), and system programmers need to set the
values of PA and CA explicitly.
If WA is ON (1), after CA has reached the end of
page (CA=101), CA will be rest to 0 and PA will
increment or decrement, depending on the
setting of Page Increment Direction (PID, AC[2]).
When PA reaches the boundary of RAM (i.e. PA
= 0 or 7), PA will be wrapped around to the other
end of RAM and continue.
I
CON
D
ATA
A
DDRESSING
The Icon Page is addressed by explicitly setting
PA to 8 (the 9
page). When addressing Icon
page, auto wrap-around will be suspended and
CA will stop when CA reaches 102.