
U
LTRA
C
HIP
High-Voltage Mixed-Signal IC
2000
10
Product Specifications
LCD V
OLTAGE
S
ETTINGS
M
ULTIPLEX
R
ATES
Two multiplex rates are supported in UC1602I: 65
or 49. The default is 65 and it can be changed by
programming.
B
IAS
S
ELECTION
Bias Ratio (
BR
) is defined as the ratio between
V
LCD
and V
D
, i.e.
BR = V
LCD
/V
D
, where V
D
is the
SEG data signal and its value is | V
B1+
– V
B1–
|
The optimum
Bias Ratio
can be calculated by:
1
+
Mux
UC1602I supports four bias ratios as below.
BR
0
6
1
7
2
8
3
9
Bias Ratio
Table 2:
BR vs. Mux rates
BR and MR can both be changed dynamically by
software programming.
V
D
G
ENERATION
V
D
is generated internally by UC106. The value of
V
D
is determined by three control registers:
GN
(Gain),
PM
(Potential Meter), TC (Temperature
Compensation) with the following relationship:
PM
D
V
Gain
V
×
=
where V
PM
is the output of an internal Electronic
Potential Meter. The maximum value for V
D
depends on the value of V
DD2
. At V
DD2
= 2.4V, V
D
should be kept under 1.2V.
The value of V
PM
is given by:
REF
PM
V
PM
V
×
+
=
1200
600
The value of
Gain
is controlled by GN[1:0]. Their
relationship is shown below:
GN[1:0]
Gain
00
1.35 1.49 1.64 1.81
01
10
11
Table 3:
Gain vs. GN value
V
REF
T
EMPERATURE
C
OMPENSATION
V
REF
is a temperature compensated reference
voltage. V
REF
increases automatically as ambient
temperature cools down.
Four (4) different temperature compensated V
REF
can be selected via pin wiring. The compensation
coefficient is given by the following table:
TC[1:0]
0
1
2
3
% per
o
C
0.0
–0.05 –0.10 –0.20
Table 4:
Temperature Compensation
For all TC values, V
REF
are normalized to 1.2V at
25
C.
V
LCD
S
ELECTION
V
LCD
may be supplied either by internal charge
pump or by external power supply. The source of
V
LCD
is controlled by PC[2:1].
When V
LCD
is generated internally its value has
the following relationship with V
D
:
D
LCD
V
BiasRatio
V
×
=
Given V
REF
= 1.2V at 25
o
C, V
LCD
becomes:
2
×
1200
600
+
×
×
PM
Gain
BiasRatio
V
LCD
(1)
When PM=0, then equation (1) becomes:
6
×
×
Gain
BiasRatio
V
LCD
(1b)
L
OAD
D
RIVING
S
TRENGTH
UC106’s drivers and power supply circuits are
designed to handle panel capacitance load of
25nF at V
LCD
=9V when V
DD2
>= 2.4V.
UC1602I load driving strength is sensitive to ITO
impedance of power supply circuits (V
DD2
, V
SS2
,
V
B0/B1
, V
LCD
.) Be sure to minimize the resistance
of these ITO traces for COG applications.
P
OWER
S
UPPLY
C
ONFIGURATION
UC1602I has built-in charge pump with on-chip
pumping capacitors. The number of pump stages
used can be programmed by setting PC[2:1]
register. Make sure the chip is in Reset mode
before changing the value of PC[2:0].
Given the same display quality, the lower the
PC[2:1] setting the more efficient is UC1602I, but
the weaker is the driving strength. In application,
designer is recommended to verify the design
with the highest setting first before trying lower
settings to achieve better efficiency.
Due to the use of fully embedded power supply,
built-in power ready detector, and drain circuit,
there is no rigid power up or power down
sequences for UC1602I controllers when using
internal V
LCD
generator.
On the other hand, caution must be exercised
when external V
LCD
source is used. The general
rule of thumb is to make sure Display Enable is