
UC1602I
65x102 Matrix LCD Controller-Drivers
Rev. 0.54 10/12/2001
13
H
OST
I
NTERFACE
UC1602I series supports several parallel and
serial host interface formats.
Bus
Bus Type
8080
6800
4-wire (S8)
2-wire (I
2
C)
Access
R/W
R/W
W
R/W
Parallel
Serial
Table 5:
Host interfaces Choices
System designers can use either the 8-bit parallel
bus to achieve the high data transfer rate, or use
serial bus to create LCD modules with as few as
9-pin connectors.
P
ARALLEL
I
NTERFACE
It is possible to interface UC1602I controllers
directly to either an 8080-style MPU bus or a
6800-style MCU bus with the following
connection.
Bus Type
8080
WR0
___ ___
WR
_ _
R/W
WR1
___ __
RD
E
6800
Table 6:
MPU bus control signal interface
The timing relationship between UC1602I internal
control signal RD, WR and their associated bus
actions are shown in the figure below. The
generation of UC1602I internal bus control
signals WR and RD is shown in the table below.
___ ___
WR
8080
WR0
6800
!(WR1 & !WR0)
Bus Type
___ __
RD
WR1
!(WR1 & WR0)
Table 7:
WR and RD signal generation
D
ISPLAY
RAM D
ATA
T
RANSFER
UC1602I Display Data RAM (RAM) read interface
is implemented as a two-stage pipe-line. This
architecture requires that, every time memory
address is modified, either in parallel mode or
serial mode, all three commands (
Set CA-LSB,
Set CA-MSB, Set PA
) need to be issued, and a
dummy read cycle need to be performed before
the actual data can propagate through the pipe-
line and be read from data port D[7:0].
There is no pipeline in write interface of RAM,
and the data is transferred directly from data bus
buffer to RAM.
CD
___
WR
__
RD
D[7:0]
Write
Read
Bus
Holder
Column
Address
L
LSB
D
L
D
L+K
C
MSB
C
LSB
Dummy
D
C
D
C+1
M
MSB
M
LSB
D
L
D
L+K
Dummy
D
C
D
C+1
L
L+K
L+K+1
C
C+1
C+2
C+3
M
Figure 5:
Parallel Interface & Related Internal Signals