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參數(shù)資料
| 型號(hào)： | UC1602I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 65x102 Matrix LCD Controller-Driver |
| 中文描述： | 65x102矩陣LCD控制器驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 22/38頁 |
| 文件大?。?/td> | 723K |
| 代理商： | UC1602I |
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U
LTRA
C
HIP
High-Voltage Mixed-Signal IC
2000
20
Product Specifications
R
ESET
& P
OWER
M
ANAGEMENT
T
YPES OF
R
ESET
UC1602I has two different types of Reset:
Power-ON-Reset
and
System-Reset
.
Power-ON-Reset
is performed right after V
DD1
is
connected to power.
Power-On-Reset
will first
wait for about 12mS, depending on the time
required for V
DD
to stabilize, and then trigger the
System Reset
.
System Reset
can also be activated by software
command or by connecting RST pin to ground.
In the following discussions, Reset means
System Reset
.
R
ESET
S
TATUS
When UC1602I enters RESET sequence:
All non-pin configurable control registers will
be reset to their default values.
All pin configurable control registers will be
reset according to their configuration pins.
Operation mode will be “Reset”
System Status bits RS and BZ will stay as
“1” until the Reset process is completed (for
a duration of 3~5uS).
Refer to Control Registers for details of control
flags and their default values. Refer to Pin
Description for configuration pin definitions.
When RS=1, only status read command is
processed by UC106. All other commands are
ignored.
Once entered Reset mode, all control registers
will be reset to their default values and capacitors
will be discharged. In general it is necessary to
set up control registers before transition out of
the Reset mode.
O
PERATION
M
ODES
UC1602I has three operating modes (OM):
Reset, Normal, Sleep.
Mode
OM
Reset
00
Active
OFF
OFF
OFF
ON
Sleep Normal
10
Active
OFF
OFF
OFF
OFF
11
Host Interface
Clock
LCD Drivers
Charge Pump
Draining Circuit
Active
ON
ON
ON
OFF
Table 11:
Operating Modes
C
HANGING
O
PERATION
M
ODE
Two commands will initiate OM transitions:
Set Display Enable
, and
System Reset
.
Action
Mode
Normal
Sleep
OM
11
10
Set Display Enable “ON”
Set Display Enable “OFF”
Reset command
RST_ pin pulled “L”
Power ON reset
Reset
00
Table 12:
OM changes
When DC[2] is modified by
Set Display Enable
,
OM will be updated automatically. There is no
other action required to enter power saving mode.
For maximum energy utilization, Sleep mode is
designed to retain charges stored in external
capacitors C
B0
, C
B1
and C
LCD
. To drain these
capacitors, use Reset command to activate the
on-chip draining circuit.
OM changes are synchronized with the edges of
UC1602I internal clock. To ensure consistent
system states, wait at least 10uS after
System
Reset
or
Set Display Enable
command.
E
XITING
P
OWER
S
AVE
M
ODES
UC1602I contains internal logic to check whether
V
LCD
and V
D
is ready before releasing row and
column drivers from their OFF states. When
exiting Sleep Mode and Reset Mode, column and
row drivers will not be activated until UC1602I
internal voltage sources are restored to their
proper values.
P
OWER
-U
P
S
EQUENCE
UC1602I power-up sequence is simplified by
built-in “Power Ready” flags and by the automatic
invocation of
System-Reset
command after
Power-ON-Reset
. System programmer are only
required to wait 4~6 ms before starting to issue
commands to UC106. No additional commands
or waits are required between enabling of the
charge pump, turning on the display drivers,
writing to RAM or any other commands.
P
OWER
-D
OWN
S
EQUENCE
To prevent the charge stored in capacitors C
B+
,
C
B–
, and C
LCD
from damaging the LCD when V
DD
is switched off, use Reset mode to enable the
built-in charge draining circuit to discharge these
external capacitors.
UC1602I draining resistance is 1K for both V
LCD
and V
B+
. It is recommended to wait
3
x
RC
for
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