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參數(shù)資料
| 型號： | TTSI1K16T3TL |
| 英文描述： | 1024-Channel, 16-Highway Time-Slot Interchanger |
| 中文描述： | 1024通道，16道時隙交換器 |
| 文件頁數(shù)： | 55/64頁 |
| 文件大?。?/td> | 1110K |
| 代理商： | TTSI1K16T3TL |
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Preliminary Data Sheet
February 1999
TTSI1K16T
1024-Channel, 16-Highway Time-Slot Interchanger
55
Lucent Technologies Inc.
Timing Characteristics
(continued)
5-7063(F)r.2
Figure 16. Asynchronous Read Cycle Timing Using DT Handshake
5-7064(F)r.2
Figure 17. Asynchronous Write Cycle Timing Using DT Handshake
Table 47. Asynchronous Read and Write Interface Timing Using DT Handshake
* CS asynchronously controls the output enable of D[7—0] and DT. The delay from CS to the output enable of DT is equivalent to the delay
from AS or DS to DT. Therefore, in order to guarantee that DT is driven high before being 3-stated, a CS hold time is required (t3). If this tim-
ing cannot be met, then there are two options. One, disconnect DT and rely on wait-states to terminate the cycle. The read or write cycle will
be completed by the device 183 ns after the start of the cycle, which is defined by CS, AS, and DS all being active. The second option is to
use an external pull-up on DT to pull DT high within the timing requirements of the microprocessor.
Symbol
Description
Min
Max
Unit
t1
t2
t3
t4
t5
t6
t7
t8
A[14—0] or R/W Setup to AS
A[14—0] or R/W Hold from AS
CS Hold from AS or DS
DT Output Delay from AS or DS (C
L
= 50 pF)
DT or D[7—0] High-impedance from CS (C
L
= 50 pF)
D[7—0] Input Setup to DS (C
L
= 50 pF)
D[7—0] Input Hold from DS (C
L
= 50 pF)
D[7—0] Output Setup Prior to DT Output (C
L
= 50 pF)
0
0
4*
3*
—
0
0
0
—
—
—
8*
8.5*
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
D[7—0]
AS
DS
DT
READ DATA
t4
t4
t8
CS
A[14—0]
READ ADDRESS
t3
R/W
t1
t2
t5
HIGH IMPEDANCE
D[7—0]
AS
DS
DT
WRITE DATA
t4
t6
CS
A[14—0]
WRITE ADDRESS
t3
R/W
t1
t2
t7
t4
t5
HIGH IMPEDANCE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TTSI1K16T | 1024-Channel, 16-Highway Time-Slot Interchanger(1024通道、16路干線時隙交換機) |
| TTSI2K32T | 2048-Channel, 32-Highway Time-Slot Interchanger |
| TTSI2K32T3BAL | 2048-Channel, 32-Highway Time-Slot Interchanger |
| TTSI2K32T | 2048-Channel, 32-Highway Time-Slot Interchanger(2048通道、32路干線時隙交換機) |
| TTSI4K32T | 4096-Channel, 32-Highway Time-Slot Interchanger |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TTSI1K16T3TL-DB | 制造商:LSI 功能描述: 制造商:LSI Corporation 功能描述: |
| TTSI2K32T | 制造商:AGERE 制造商全稱:AGERE 功能描述:2048-Channel, 32-Highway Time-Slot Interchanger |
| TTSI2K32T3BAL | 制造商:AGERE 制造商全稱:AGERE 功能描述:2048-Channel, 32-Highway Time-Slot Interchanger |
| TTSI4K32T | 制造商:AGERE 制造商全稱:AGERE 功能描述:4096-Channel, 32-Highway Time-Slot Interchanger |
| TTSI4K32T3BAL | 制造商:AGERE 制造商全稱:AGERE 功能描述:4096-Channel, 32-Highway Time-Slot Interchanger |
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